 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| REJ09B0213-0300 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8/300H Series Software Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series Rev. 3.00 Revision Date: Dec 13, 2004 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 3.00 Dec 13, 2004 page ii of xiv General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Address Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these address. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 3.00 Dec 13, 2004 page iii of xiv Rev. 3.00 Dec 13, 2004 page iv of xiv Preface The H8/300H Series is built around a 32-bit H8/300H CPU core with sixteen 16-bit registers, a concise, optimized instruction set designed for high-speed operation, and a 16-Mbyte linear address space. For easy migration from the H8/300 Series, the instruction set is upwardcompatible with the H8/300 Series at the object-code level. Programs coded in the high-level language C can be compiled to high-speed executable code. This manual gives details of the H8/300H CPU instructions and can be used with all microcontrollers in the H8/300H Series. For hardware details, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page v of xiv Rev. 3.00 Dec 13, 2004 page vi of xiv Main Revisions for this Edition Item All Page Revisions (See Manual for Details) All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names changed to Renesas Technology Corp. Designation for categories changed from "series" to "group" Rev. 3.00 Dec 13, 2004 page vii of xiv Rev. 3.00 Dec 13, 2004 page viii of xiv Contents Section 1 1.1 CPU .................................................................................................................... 1.2 1.3 1.4 1.5 1.6 Overview ........................................................................................................................... 1.1.1 Features ................................................................................................................ 1.1.2 Differences from H8/300 CPU............................................................................. CPU Operating Modes ...................................................................................................... Address Space ................................................................................................................... Register Configuration ...................................................................................................... 1.4.1 Overview .............................................................................................................. 1.4.2 General Registers ................................................................................................. 1.4.3 Control Registers.................................................................................................. 1.4.4 Initial Register Values .......................................................................................... Data Formats ..................................................................................................................... 1.5.1 General Register Data Formats ............................................................................ 1.5.2 Memory Data Formats ......................................................................................... Instruction Set ................................................................................................................... 1.6.1 Overview .............................................................................................................. 1.6.2 Instructions and Addressing Modes ..................................................................... 1.6.3 Tables of Instructions Classified by Function ...................................................... 1.6.4 Basic Instruction Formats..................................................................................... 1.6.5 Addressing Modes and Effective Address Calculation ........................................ 1 1 1 2 3 7 8 8 9 10 11 12 12 14 15 15 16 18 26 28 Section 2 2.1 Instruction Descriptions................................................................................ 35 35 36 37 38 38 39 40 41 42 43 44 45 46 47 48 2.2 Tables and Symbols........................................................................................................... 2.1.1 Assembler Format ................................................................................................ 2.1.2 Operation.............................................................................................................. 2.1.3 Condition Code .................................................................................................... 2.1.4 Instruction Format ................................................................................................ 2.1.5 Register Specification........................................................................................... 2.1.6 Bit Data Access in Bit Manipulation Instructions ................................................ Instruction Descriptions .................................................................................................... 2.2.1 (1) ADD (B) .......................................................................................................... 2.2.1 (2) ADD (W) ......................................................................................................... 2.2.1 (3) ADD (L) .......................................................................................................... 2.2.2 ADDS .............................................................................................................. 2.2.3 ADDX ............................................................................................................. 2.2.4 (1) AND (B) .......................................................................................................... 2.2.4 (2) AND (W) ......................................................................................................... Rev. 3.00 Dec 13, 2004 page ix of xiv 2.2.4 (3) 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.2.13 2.2.14 2.2.15 2.2.16 2.2.17 2.2.18 2.2.19 2.2.20 2.2.21 2.2.22 (1) 2.2.22 (2) 2.2.22 (3) 2.2.23 2.2.24 2.2.25 (1) 2.2.25 (2) 2.2.25 (3) 2.2.26 (1) 2.2.26 (2) 2.2.26 (3) 2.2.27 (1) 2.2.27 (2) 2.2.28 (1) 2.2.28 (2) 2.2.29 (1) 2.2.29 (2) 2.2.30 (1) 2.2.30 (2) 2.2.31 (1) 2.2.31 (2) 2.2.31 (3) AND (L) .......................................................................................................... 49 ANDC.............................................................................................................. 50 BAND.............................................................................................................. 51 Bcc................................................................................................................... 52 BCLR............................................................................................................... 54 BIAND ............................................................................................................ 56 BILD................................................................................................................ 57 BIOR ............................................................................................................... 58 BIST ................................................................................................................ 59 BIXOR............................................................................................................. 60 BLD ................................................................................................................. 61 BNOT .............................................................................................................. 62 BOR................................................................................................................. 64 BSET ............................................................................................................... 65 BSR ................................................................................................................. 67 BST.................................................................................................................. 69 BTST ............................................................................................................... 70 BXOR.............................................................................................................. 72 CMP (B) .......................................................................................................... 73 CMP (W) ......................................................................................................... 74 CMP (L) .......................................................................................................... 75 DAA ................................................................................................................ 76 DAS ................................................................................................................. 78 DEC (B)........................................................................................................... 80 DEC (W).......................................................................................................... 81 DEC (L) ........................................................................................................... 82 DIVXS (B)....................................................................................................... 83 DIVXS (W) ..................................................................................................... 85 DIVXS............................................................................................................. 87 DIVXU (B)...................................................................................................... 91 DIVXU (W)..................................................................................................... 92 EEPMOV (B) .................................................................................................. 97 EEPMOV (W) ................................................................................................. 98 EXTS (W)........................................................................................................ 100 EXTS (L) ......................................................................................................... 101 EXTU (W) ....................................................................................................... 102 EXTU (L) ........................................................................................................ 103 INC (B)............................................................................................................ 104 INC (W)........................................................................................................... 105 INC (L) ............................................................................................................ 106 Rev. 3.00 Dec 13, 2004 page x of xiv 2.2.32 2.2.33 2.2.34 (1) 2.2.34 (2) 2.2.35 (1) 2.2.35 (2) 2.2.35 (3) 2.2.35 (4) 2.2.35 (5) 2.2.35 (6) 2.2.35 (7) 2.2.35 (8) 2.2.35 (9) 2.2.36 2.2.37 2.2.38 (1) 2.2.38 (2) 2.2.39 (1) 2.2.39 (2) 2.2.40 (1) 2.2.40 (2) 2.2.40 (3) 2.2.41 2.2.42 (1) 2.2.42 (2) 2.2.42 (3) 2.2.43 (1) 2.2.43 (2) 2.2.43 (3) 2.2.44 2.2.45 (1) 2.2.45 (2) 2.2.46 (1) 2.2.46 (2) 2.2.47 (1) 2.2.47 (2) 2.2.47 (3) 2.2.48 (1) 2.2.48 (2) 2.2.48 (3) JMP.................................................................................................................. 107 JSR................................................................................................................... 108 LDC (B)........................................................................................................... 110 LDC (W).......................................................................................................... 111 MOV (B) ......................................................................................................... 113 MOV (W) ........................................................................................................ 114 MOV (L).......................................................................................................... 115 MOV (B) ......................................................................................................... 116 MOV (W) ........................................................................................................ 118 MOV (L).......................................................................................................... 120 MOV (B) ......................................................................................................... 122 MOV (W) ........................................................................................................ 124 MOV (L).......................................................................................................... 126 MOVFPE......................................................................................................... 128 MOVTPE......................................................................................................... 129 MULXS (B)..................................................................................................... 130 MULXS (W).................................................................................................... 131 MULXU (B) .................................................................................................... 132 MULXU (W) ................................................................................................... 133 NEG (B) .......................................................................................................... 134 NEG (W) ......................................................................................................... 135 NEG (L)........................................................................................................... 136 NOP ................................................................................................................. 137 NOT (B) .......................................................................................................... 138 NOT (W) ......................................................................................................... 139 NOT (L)........................................................................................................... 140 OR (B) ............................................................................................................. 141 OR (W) ............................................................................................................ 142 OR (L) ............................................................................................................. 143 ORC................................................................................................................. 144 POP (W) .......................................................................................................... 145 POP (L)............................................................................................................ 146 PUSH (W) ....................................................................................................... 147 PUSH (L)......................................................................................................... 148 ROTL (B) ........................................................................................................ 149 ROTL (W) ....................................................................................................... 150 ROTL (L) ........................................................................................................ 151 ROTR (B) ........................................................................................................ 152 ROTR (W) ....................................................................................................... 153 ROTR (L) ........................................................................................................ 154 Rev. 3.00 Dec 13, 2004 page xi of xiv 2.3 2.4 2.5 2.6 2.7 2.8 2.2.49 (1) ROTXL (B) ..................................................................................................... 155 2.2.49 (2) ROTXL (W) .................................................................................................... 156 2.2.49 (3) ROTXL (L)...................................................................................................... 157 2.2.50 (1) ROTXR (B) ..................................................................................................... 158 2.2.50 (2) ROTXR (W) .................................................................................................... 159 2.2.50 (3) ROTXR (L) ..................................................................................................... 160 2.2.51 RTE ................................................................................................................. 161 2.2.52 RTS.................................................................................................................. 163 2.2.53 (1) SHAL (B) ........................................................................................................ 164 2.2.53 (2) SHAL (W) ....................................................................................................... 165 2.2.53 (3) SHAL (L) ........................................................................................................ 166 2.2.54 (1) SHAR (B) ........................................................................................................ 167 2.2.54 (2) SHAR (W) ....................................................................................................... 168 2.2.54 (3) SHAR (L) ........................................................................................................ 169 2.2.55 (1) SHLL (B)......................................................................................................... 170 2.2.55 (2) SHLL (W)........................................................................................................ 171 2.2.55 (3) SHLL (L) ......................................................................................................... 172 2.2.56 (1) SHLR (B)......................................................................................................... 173 2.2.56 (2) SHLR (W) ....................................................................................................... 174 2.2.56 (3) SHLR (L)......................................................................................................... 175 2.2.57 SLEEP ............................................................................................................. 176 2.2.58 (1) STC (B) ........................................................................................................... 177 2.2.58 (2) STC (W) .......................................................................................................... 178 2.2.59 (1) SUB (B) ........................................................................................................... 180 2.2.59 (2) SUB (W).......................................................................................................... 182 2.2.59 (3) SUB (L) ........................................................................................................... 183 2.2.60 SUBS ............................................................................................................... 184 2.2.61 SUBX .............................................................................................................. 185 2.2.62 TRAPA ............................................................................................................ 186 2.2.63 (1) XOR (B) .......................................................................................................... 187 2.2.63 (2) XOR (W) ......................................................................................................... 188 2.2.63 (3) XOR (L) .......................................................................................................... 189 2.2.64 XORC.............................................................................................................. 190 Instruction Set Summary ................................................................................................... 191 Instruction Codes............................................................................................................... 205 Operation Code Map ......................................................................................................... 213 Number of States Required for Instruction Execution....................................................... 217 Condition Code Modification............................................................................................ 228 Bus Cycles During Instruction Execution ......................................................................... 233 Rev. 3.00 Dec 13, 2004 page xii of xiv Section 3 3.1 3.2 3.3 3.4 3.5 3.6 Processing States ............................................................................................ 245 Overview ........................................................................................................................... 245 Program Execution State ................................................................................................... 246 Exception-Handling State.................................................................................................. 246 3.3.1 Types of Exception Handling and Their Priority ................................................. 247 3.3.2 Exception-Handling Sequences............................................................................ 248 Bus-Released State ............................................................................................................ 250 Reset State ......................................................................................................................... 250 Power-Down State............................................................................................................. 250 3.6.1 Sleep Mode........................................................................................................... 250 3.6.2 Software Standby Mode ....................................................................................... 250 3.6.3 Hardware Standby Mode...................................................................................... 251 Section 4 4.1 4.2 4.3 4.4 Basic Timing.................................................................................................... 253 Overview ........................................................................................................................... 253 On-Chip Memory (RAM, ROM)....................................................................................... 253 On-Chip Supporting Modules ........................................................................................... 255 External Data Bus.............................................................................................................. 256 Rev. 3.00 Dec 13, 2004 page xiii of xiv Rev. 3.00 Dec 13, 2004 page xiv of xiv Section 1 CPU Section 1 CPU 1.1 Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 1.1.1 Features The H8/300H CPU has the following features. * Upward-compatible with H8/300 CPU Can execute H8/300 object programs * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-two basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, or @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space * High-speed operation All frequently-used instructions execute in two to four states Maximum clock frequency: 16 MHz 8/16/32-bit register-register add/subtract: 125 ns 8 x 8-bit register-register multiply: 875 ns Rev. 3.00 Dec 13, 2004 page 1 of 258 REJ09B0213-0300 Section 1 CPU 16 / 8-bit register-register divide: 875 ns 16 x 16-bit register-register multiply: 1375 ns 32 / 16-bit register-register divide: 1375 ns * Two CPU operating modes Normal mode Advanced mode * Low-power mode Transition to power-down state by SLEEP instruction 1.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8/300H CPU has the following enhancements. * More general registers Eight 16-bit registers have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Signed multiply/divide instructions and other instructions have been added. Rev. 3.00 Dec 13, 2004 page 2 of 258 REJ09B0213-0300 Section 1 CPU 1.2 CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. The mode is selected at the mode pins of the microcontroller. For further information, refer to the relevant hardware manual. Maximum 64 kbytes, program and data areas combined Normal mode CPU operating modes Advanced mode Maximum 16 Mbytes, program and data areas combined Figure 1.1 CPU Operating Modes (1) Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed, as in the H8/300 CPU. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit data registers, or they can be combined with the general registers (R0 to R7) for use as 32-bit data registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (R0 to R7) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register will be affected. Instruction Set: All additional instructions and addressing modes of the H8/300 CPU can be used. If a 24-bit effective address (EA) is specified, only the lower 16 bits are used. Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 1.2). The exception vector table differs depending on the microcontroller, so see the microcontroller hardware manual for further information. Rev. 3.00 Dec 13, 2004 page 3 of 258 REJ09B0213-0300 Section 1 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 Reset exception vector Reserved for system use Exception vector table Exception vector 1 Exception vector 2 Figure 1.2 Exception Vector Table (normal mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. Stack Structure: When the program counter (PC) is pushed on the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed on the stack in exception handling, they are stored in the same way as in the H8/300 CPU. See figure 1.3. (a) Subroutine branch (b) Exception handling SP PC (16 bits) SP CCR CCR* PC (16 bits) Note: * Ignored at return. Figure 1.3 Stack Structure (normal mode) Rev. 3.00 Dec 13, 2004 page 4 of 258 REJ09B0213-0300 Section 1 CPU (2) Advanced Mode In advanced mode the exception vector table and stack structure differ from the H8/300 CPU. Address Space: Up to 16 Mbytes can be accessed linearly. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit data registers, or they can be combined with the general registers (R0 to R7) for use as 32-bit data registers. When a 32-bit register is used as an address register, the upper 8 bits are ignored. Instruction Set: All additional instructions and addressing modes of the H8/300H can be used. Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 1.4). The exception vector table differs depending on the microcontroller, so see the relevant hardware manual for further information. H'000000 Don't care Reset exception vector H'000003 H'000004 Exception vector table Reserved for system use H'00000B H'00000C Don't care Exception vector Figure 1.4 Exception Vector Table (advanced mode) Rev. 3.00 Dec 13, 2004 page 5 of 258 REJ09B0213-0300 Section 1 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, of which the lower 24 bits are the branch address. Branch addresses can be stored in the top area from H'000000 to H'0000FF. Note that this area is also used for the exception vector table. Stack Structure:When the program counter (PC) is pushed on the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed on the stack in exception handling, they are stored as shown in figure 1.5. (a) Subroutine branch (b) Exception handling SP Reserved PC (24 bits) SP CCR PC (24 bits) Figure 1.5 Stack Structure (advanced mode) Rev. 3.00 Dec 13, 2004 page 6 of 258 REJ09B0213-0300 Section 1 CPU 1.3 Address Space Figure 1.6 shows a memory map of the H8/300H CPU. (a) Normal mode (b) Advanced mode H'0000 H'000000 H'FFFF H'FFFFFF Figure 1.6 Memory Map Rev. 3.00 Dec 13, 2004 page 7 of 258 REJ09B0213-0300 Section 1 CPU 1.4 1.4.1 Register Configuration Overview The H8/300H CPU has the internal registers shown in figure 1.7. There are two types of registers: general and extended registers, and control registers. General registers (Rn) and extended registers (En) 15 E0 E1 E2 E3 E4 E5 E6 SP E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control registers (CR) 23 PC 76543210 CCR I U H U N Z V C Legend: SP: Stack pointer PC: Program counter CCR: Condition code register Interrupt mask bit I: User bit or interrupt mask bit U: Half-carry flag H: Negative flag N: Zero flag Z: Overflow flag V: Carry flag C: 0 Figure 1.7 CPU Registers Rev. 3.00 Dec 13, 2004 page 8 of 258 REJ09B0213-0300 Section 1 CPU 1.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 1.8 illustrates the usage of the general registers. The usage of each register can be selected independently. Address registers * 32-bit registers * 16-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H) * 8-bit registers Figure 1.8 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 1.9 shows the stack. Rev. 3.00 Dec 13, 2004 page 9 of 258 REJ09B0213-0300 Section 1 CPU Free area SP (ER7) Stack area Figure 1.9 Stack 1.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0. (2) Condition Code Register (CCR) This 8-bit register contains internal CPU status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7--Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. Bit 6--User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details see the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 10 of 258 REJ09B0213-0300 Section 1 CPU Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4--User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3--Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to the detailed descriptions of the instructions starting in section 2.2.1. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 1.4.4 Initial Register Values When the CPU is reset, the program counter (PC) is loaded from the vector table and the I bit in the condition-code register (CCR) is set to 1. The other CCR bits and the general registers and extended registers are not initialized. In particular, the stack pointer (extended register E7 and general register R7) is not initialized. The stack pointer must therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 3.00 Dec 13, 2004 page 11 of 258 REJ09B0213-0300 Section 1 CPU 1.5 Data Formats The H8/300H CPU can process 1-bit, 4-bit, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 1.5.1 General Register Data Formats Figure 1.10 shows the data formats in general registers. Data type Register number Data format 1-bit data RnH 7 0 76543210 Don't care 1-bit data RnL Don't care 7 0 76543210 4-bit BCD data RnH 7 Upper 43 Lower 0 Don't care 4-bit BCD data RnL Don't care 7 Upper 43 Lower 0 Byte data RnH 7 MSB 0 Don't care LSB 7 Don't care Byte data RnL 0 LSB MSB Figure 1.10 General Register Data Formats Rev. 3.00 Dec 13, 2004 page 12 of 258 REJ09B0213-0300 Section 1 CPU Word data Rn 15 MSB 0 LSB Word data 15 MSB Longword data 31 MSB En 0 LSB ERn 16 15 En Rn 0 LSB Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 1.10 General Register Data Formats (cont) Rev. 3.00 Dec 13, 2004 page 13 of 258 REJ09B0213-0300 Section 1 CPU 1.5.2 Memory Data Formats Figure 1.11 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data format Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 1.11 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size. Rev. 3.00 Dec 13, 2004 page 14 of 258 REJ09B0213-0300 Section 1 CPU 1.6 1.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified by function in table 1.1. For a detailed description of each instruction see section 2.2, Instruction Descriptions. Table 1.1 Instruction Classification Function Data transfer Arithmetic operations Instructions MOV, PUSH* , POP* , MOVTPE, MOVFPE 1 2 Number 3 18 ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST 2 Bcc* , JMP, BSR, JSR, RTS EEPMOV Total 62 types Logic operations Shift Bit manipulation Branch System control Block data transfer 4 8 14 5 1 TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9 Notes: The shaded instructions are not present in the H8/300 instruction set. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the generic designation of a conditional branch instruction. Rev. 3.00 Dec 13, 2004 page 15 of 258 REJ09B0213-0300 Section 1 CPU 1.6.2 Instructions and Addressing Modes Table 1.2 indicates the instructions available in the H8/300H CPU. Table 1.2 Instruction Set Overview Addressing Modes @ERn+/@-ERn @(d:16,ERn) @(d:24,ERn) @(d:8,PC) Function Instruction @ERn #xx @(d:16,PC) @@aa:8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- @aa:16 @aa:24 @aa:8 Rn Data transfer MOV POP, PUSH MOVFPE, MOVTPE BWL BWL BWL BWL BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B BWL BWL -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- WL Arithmetic operations ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS BWL BWL WL B -- -- -- -- -- -- -- BWL B L*1 BWL B BW BW BWL WL -- -- -- -- -- -- -- -- -- -- -- -- -- -- Logic operations AND, OR, XOR NOT BWL BWL -- -- -- BWL BWL B Shift Bit manipulation Rev. 3.00 Dec 13, 2004 page 16 of 258 REJ09B0213-0300 -- Section 1 CPU Addressing Modes @ERn+/@-ERn @(d:16,ERn) @(d:24,ERn) @(d:8,PC) Function Instruction @ERn #xx @(d:16,PC) @@aa:8 -- -- -- -- -- -- -- -- -- -- -- @aa:16 @aa:24 @aa:8 Rn Branch Bcc, BSR JMP, JSR RTS -- -- -- -- -- -- B -- B -- -- -- -- -- -- B B -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- *2 -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- W W -- System control TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Block data transfer EEPMOV.B EEPMOV.W Legend: B: Byte W: Word L: Longword : Newly added instruction in H8/300H CPU Notes: 1. The operand size of the ADDS and SUBS instructions of the H8/300H CPU has been changed to longword size. (In the H8/300 CPU it was word size.) 2. Because of its larger address space, the H8/300H CPU uses a 24-bit absolute address for the JMP and JSR instructions. (The H8/300 CPU used 16 bits.) Rev. 3.00 Dec 13, 2004 page 17 of 258 REJ09B0213-0300 -- Section 1 CPU 1.6.3 Tables of Instructions Classified by Function Table 1.3 summarizes the instructions in each functional category. The notation used in table 1.3 is defined next. Operation Notation Rd Rs Rn ERn (EAd) (EAs) CCR N Z V C PC SP #IMM disp + - x / :3/:8/:16/:24 General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Condition code register N (negative) bit of CCR Z (zero) bit of CCR V (overflow) bit of CCR C (carry) bit of CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Not 3-, 8-, 16-, or 24-bit length Note: * General registers include 8-bit registers (R0H/R0L to R7H/R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 3.00 Dec 13, 2004 page 18 of 258 REJ09B0213-0300 Section 1 CPU Table 1.3 Type Data transfer Instructions Classified by Function Instruction MOV Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) Rd Moves external memory contents (addressed by @aa:16) to a general register in synchronization with an E clock. MOVTPE B Rs (EAd) Moves general register contents to an external memory location (addressed by @aa:16) in synchronization with an E clock. POP W/L @SP+ Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn @-SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. Arithmetic operations ADD SUB B/W/L Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register. Use the SUBX or ADD instruction.) ADDX SUBX B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. INC DEC B/W/L Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rev. 3.00 Dec 13, 2004 page 19 of 258 REJ09B0213-0300 Section 1 CPU Type Arithmetic operations Instruction ADDS SUBS DAA DAS B Size* L Function Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4bit BCD data. B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. MULXU B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. DIVXS B/W Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. DIVXU B/W Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. CMP B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR according to the result. NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. MULXS Rev. 3.00 Dec 13, 2004 page 20 of 258 REJ09B0213-0300 Section 1 CPU Type Arithmetic operations Instruction EXTS Size* W/L Function Rd (sign extension) Rd Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit. EXTU W/L Rd (zero extension) Rd Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by padding with zeros. Logic operations AND B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L (Rd) (Rd) Takes the one's complement of general register contents. Shift operations SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B/W/L B/W/L B/W/L B/W/L Rd (shift) Rd Performs an arithmetic shift on general register contents. Rd (shift) Rd Performs a logical shift on general register contents. Rd (rotate) Rd Rotates general register contents. Rd (rotate) Rd Rotates general register contents through the carry bit. Rev. 3.00 Dec 13, 2004 page 21 of 258 REJ09B0213-0300 Section 1 CPU Type Bit-manipulation instructions Instruction BSET Size* B Function 1 ( Rev. 3.00 Dec 13, 2004 page 22 of 258 REJ09B0213-0300 Section 1 CPU Type Bit-manipulation instructions Instruction BOR Size* B Function C ( Rev. 3.00 Dec 13, 2004 page 23 of 258 REJ09B0213-0300 Section 1 CPU Type Branching instructions Instruction Bcc Size* -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS Bcc(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 JMP BSR JSR RTS -- -- -- -- Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine. Rev. 3.00 Dec 13, 2004 page 24 of 258 REJ09B0213-0300 Section 1 CPU Type System control instructions Instruction TRAPA RTE SLEEP LDC Size* -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to the power-down state. (EAs) CCR Moves the source operand contents to the condition code register. Byte transfer is performed in the #xx:8, Rs addressing mode and word transfer in other addressing modes. STC B/W CCR (EAd) Transfers the CCR contents to a destination location. Byte transfer is performed in the Rd addressing mode and word transfer in other addressing modes. ANDC B CCR #IMM CCR Logically ANDs the condition code register with immediate data. ORC B CCR #IMM CCR Logically ORs the condition code register with immediate data. XORC B CCR #IMM CCR Logically exclusive-ORs the condition code register with immediate data. NOP -- PC + 2 PC Only increments the program counter. Rev. 3.00 Dec 13, 2004 page 25 of 258 REJ09B0213-0300 Section 1 CPU Type Block data transfer instruction Instruction EEPMOV.B Size* -- Function if R4L 0 then Repeat @ER5 + @ER6 + R4L - 1R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5 + @ER6 + R4 - 1R4L Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and R6. R4L or R4: size of block (bytes) ER5: starting source address R6: starting destination address Execution of the next instruction begins as soon as the transfer is completed. Note: * Size refers to the operand size. B: Byte W: Word L: Longword EEPMOV.W -- 1.6.4 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates the function of the instruction, the effective address, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A 24-bit address or a displacement is treated as 32-bit data in which the first 8 bits are 0. Rev. 3.00 Dec 13, 2004 page 26 of 258 REJ09B0213-0300 Section 1 CPU Condition Field: Specifies the branching condition of Bcc instructions. Figure 1.12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD. Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) rn rm MOV @(d:16, Rn), Rm (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA @(d:8, PC) Figure 1.12 Instruction Formats Rev. 3.00 Dec 13, 2004 page 27 of 258 REJ09B0213-0300 Section 1 CPU 1.6.5 Addressing Modes and Effective Address Calculation (1) Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 1.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute (8-bit) addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 1.4 No. 1 2 3 4 5 6 7 8 Addressing Modes Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:24,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 1 Register Direct--Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2 Register Indirect--@ERn: The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of a memory operand. 3 Register Indirect with Displacement--@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit displacement contained in the instruction is added to an address register (an extended register paired with a general register) specified by the register field of the instruction, and the lower 24 bits of the sum specify the address of a memory operand. A 16-bit displacement is sign-extended when added. Rev. 3.00 Dec 13, 2004 page 28 of 258 REJ09B0213-0300 Section 1 CPU 4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn: * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the resulting register value should be even. 5 Absolute Address--@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space. Table 1.5 indicates the accessible address ranges. Table 1.5 Absolute Address Access Ranges Normal Mode 8 bits (@aa:8) 16 bits (@aa:16) 24 bits (@aa:24) H'FF00 to H'FFFF (65,280 to 65,535) H'0000 to H'FFFF (0 to 65,535) H'0000 to H'FFFF (0 to 65,535) Advanced Mode H'FFFF00 to H'FFFFF (16,776,960 to 16,777,215) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF (0 to 32,767, 16,744,448 to 16,777,215) H'00000 to H'FFFFF (0 to 16,777,215) For further details on the accessible range, see the relevant microcontroller hardware manual. 6 Immediate--#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in the second byte of the instruction, specifying a vector address. Rev. 3.00 Dec 13, 2004 page 29 of 258 REJ09B0213-0300 Section 1 CPU 7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit program counter (PC) contents to generate a branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 8 Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction specifies a memory operand by an 8-bit absolute address. This memory operand contains a branch address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand. The first byte is ignored and the branch address is 24 bits long. Note that the first part of the address range is also the exception vector area. For further details see the relevant microcontroller hardware manual. Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal mode (b) Advanced mode Figure 1.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing access to be performed at the address preceding the specified address. [See (2) Memory Data Formats in section 1.5.2 for further information.] (2) Effective Address Calculation Table 1.6 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Rev. 3.00 Dec 13, 2004 page 30 of 258 REJ09B0213-0300 Table 1.6 Effective Address Calculation Effective Address Calculation Effective Address (EA) Rn Operands are contents of regm and regn No. Addressing Mode and Instruction Format (1) Register direct op @ERn 31 Register contents 0 23 Regm Regn (2) Register indirect 0 op reg (3) 31 Register contents disp 31 Sign extension disp 0 0 Register indirect with displacement @(d:16, ERn) op reg 23 0 (4) 31 0 Register contents Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ 23 0 op reg 1, 2, or 4 31 Register contents 23 0 0 * Register indirect with pre-decrement @-ERn op reg Operand Size Added Value Byte Word Longword 1 2 4 1, 2, or 4 Rev. 3.00 Dec 13, 2004 page 31 of 258 REJ09B0213-0300 Section 1 CPU No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) (5) 23 H'FFFF abs 87 Absolute address 0 @aa:8 Section 1 CPU op @aa:16 23 abs 16 15 Sign extension 0 op Rev. 3.00 Dec 13, 2004 page 32 of 258 REJ09B0213-0300 23 abs 0 IMM Operand is immediate data. @aa:24 op (6) Immediate #xx:8/#xx:16/#xx:32 op No. 23 0 PC contents 23 disp 23 0 Sign extension disp 0 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) (7) Program-counter relative @(d:8, PC)/@(d:16, PC) op (8) Memory indirect @@aa:8 Normal mode abs 23 87 H'0000 abs 0 op 15 Memory contents 0 23 H'00 16 15 0 Advanced mode abs 23 H'0000 31 Memory contents 87 abs 0 23 0 0 op Rev. 3.00 Dec 13, 2004 page 33 of 258 REJ09B0213-0300 Section 1 CPU Legend: reg, regm, regn: op: disp: abs: IMM: General registers Operation field Displacement Absolute address Immediate data Section 1 CPU Rev. 3.00 Dec 13, 2004 page 34 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Section 2 Instruction Descriptions 2.1 Tables and Symbols This section explains how to read the tables describing each instruction. Note that the descriptions of some instructions extend over two pages or more. Mnemonic (full name): Gives the full and mnemonic names of the instruction. Type: Indicates the type of instruction. Operation: Describes the instruction in symbolic notation. (See section 2.1.2, Operation.) Assembly-Language Format: Indicates the assembly-language format of the instruction. (See section 2.1.1, Assembler Format.) Operand Size: Indicates the available operand sizes. Condition Code: Indicates the effect of instruction execution on the flag bits in the CCR. (See section 2.1.3, Condition Code.) Description: Describes the operation of the instruction in detail. Available Registers: Indicates which registers can be specified in the register field of the instruction. Operand Format and Number of States Required for Execution: Shows the addressing modes and instruction format together with the number of states required for execution. Notes: Gives notes concerning execution of the instruction. Rev. 3.00 Dec 13, 2004 page 35 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.1.1 Assembler Format Example: ADD. B The operand size is byte (B), word (W), or longword (L). Some instructions are restricted to a limited set of operand sizes. The symbol Symbol Rn @ERn @(d:16, ERn)/@(d:24, ERn) @ERn+, @-ERn @aa:8/16/24 #xx:8/16/32 @(d:8, PC)/@(d:16, PC) @@aa:8 Addressing Mode Register direct Register indirect Register indirect with displacement (16-bit or 24-bit) Register indirect with post-increment or pre-decrement Absolute address (8-bit, 16-bit, or 24-bit) Immediate (8-bit, 16-bit, or 32-bit) Program-counter relative (8-bit or 16-bit) Memory indirect Rev. 3.00 Dec 13, 2004 page 36 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.1.2 Operation The symbols used in the operation descriptions are defined as follows. Symbol Rd Rs Rn ERd ERs ERn (EAd) (EAs) PC SP CCR N Z V C disp + - x / ( )< > Meaning General destination register* General source register* General register* General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) Destination operand Source operand Program counter Stack pointer Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Displacement Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the right Logical AND of the operands on both sides Logical OR of the operands on both sides Logical exclusive OR of the operands on both sides Logical NOT (logical complement) Contents of effective address of the operand Note: * General registers include 8-bit registers (R0H to R7H and R0L to R7L), 16-bit registers (R0 to R7 ad E0 to E7) and 32-bit registers. Rev. 3.00 Dec 13, 2004 page 37 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.1.3 Condition Code The symbols used in the condition-code description are defined as follows. Symbol Meaning Changes according to the result of the instruction Undetermined (no guaranteed value) Always cleared to 0 Not affected by execution of the instruction Varies depending on conditions; see the notes. * 0 -- 2.1.4 Instruction Format The symbols used in the instruction format descriptions are listed below. Symbol IMM abs disp rs, rd, rn Meaning Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, or 24 bits) Displacement (8, 16, or 24 bits) Register number (4 bits. The symbol rs corresponds to operand symbols such as Rs. The symbol rd corresponds to operand symbols such as Rd. The symbol rn corresponds to the operand symbol Rn.) Register number (3 bits. The symbol ers corresponds to operand symbols such as ERs. The symbol erd corresponds to operand symbols such as ERd and @ERd. The symbol ern corresponds to the operand symbol ERn.) ers, erd, ern Rev. 3.00 Dec 13, 2004 page 38 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.1.5 Register Specification Address Register Specification: When a general register is used as an address register [@ERn, @(d:16, ERn), @(d:24, ERn), @ERn+, or @-ERn], the register is specified by a 3-bit register field (ers or erd). The lower 24 bits of the register are valid. Data Register Specification: A general register can be used as a 32-bit, 16-bit, or 8-bit data register, which is specified by a 3-bit register number. When a 32-bit register (ERn) is used as a longword data register, it is specified by a 3-bit register field (ers, erd, or ern). When a 16-bit register is used as a word data register, it is specified by a 4-bit register field (rs, rd, or rn). The lower 3 bits specify the register number. The upper bit is set to 1 to specify an extended register (En) or cleared to 0 to specify a general register (Rn). When an 8-bit register is used as a byte data register, it is specified by a 4-bit register field (rs, rd, or rn). The lower 3 bits specify the register number. The upper bit is set to 1 to specify a low register (RnL) or cleared to 0 to specify a high register (RnH). This is shown next. Address Register 32-bit Register Register Field 000 001 111 General Register ER0 ER1 ER7 16-bit Register Register Field 0000 0001 0111 1000 1001 1111 General Register R0 R1 R7 E0 E1 E7 8-bit Register Register Field 0000 0001 0111 1000 1001 1111 General Register R0H R1H R7H E0L E1L E7L Rev. 3.00 Dec 13, 2004 page 39 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.1.6 Bit Data Access in Bit Manipulation Instructions Bit data is accessed as the n-th bit (n = 0, 1, 2, 3, ..., 7) of a byte operand in a general register or memory. The bit number is given by 3-bit immediate data, or by the lower 3 bits of a general register value. Example 1: To set bit 3 in R2H to 1 BSET R1L, R2H R1L Don't care 0 1 1 Bit number R2H 0 1 1 0 0 1 0 1 Set to 1 Example 2: To load bit 5 at address H'FFFF02 into the bit accumulator BLD #5, @FFFF02 #5 H'FF02 1 0 1 0 0 1 1 0 C Load The operand size and addressing mode are as indicated for register or memory operand data. Rev. 3.00 Dec 13, 2004 page 40 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2 Instruction Descriptions The instructions are described starting in section 2.2.1. Rev. 3.00 Dec 13, 2004 page 41 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.1 (1) ADD (B) ADD (ADD binary) Operation Rd + (EAs) Rd Condition Code Add Binary Assembly-Language Format ADD.B Operand Size Byte H: Set to 1 if there is a carry at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a carry at bit 7; otherwise cleared to 0. Description This instruction adds the source operand to the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Mnemonic ADD.B ADD.B Operands #xx:8, Rd Rs, Rd Instruction Format 1st byte 8 0 rd 8 rs 2nd byte IMM rd 3rd byte 4th byte No. of States 2 2 Notes Rev. 3.00 Dec 13, 2004 page 42 of 258 REJ09B0213-0300 I -- UI -- H U -- N Z V C Section 2 Instruction Descriptions 2.2.1 (2) ADD (W) ADD (ADD binary) Operation Rd + (EAs) Rd Condition Code Add Binary Assembly-Language Format ADD.W Operand Size Word H: Set to 1 if there is a carry at bit 11; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a carry at bit 15; otherwise cleared to 0. Description This instruction adds the source operand to the contents of a 16-bit register Rd (destination operand) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Mnemonic ADD.W ADD.W Operands #xx:16, Rd Rs, Rd Instruction Format 1st byte 7 0 9 9 2nd byte 1 rs rd rd 3rd byte IMM 4th byte No. of States 4 2 Notes Rev. 3.00 Dec 13, 2004 page 43 of 258 REJ09B0213-0300 I -- UI -- H U -- N Z V C Section 2 Instruction Descriptions 2.2.1 (3) ADD (L) ADD (ADD binary) Operation ERd + (EAs) ERd Condition Code Add Binary Assembly-Language Format ADD.L Operand Size Longword H: Set to 1 if there is a carry at bit 27; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a carry at bit 31; otherwise cleared to 0. Description This instruction adds the source operand to the contents of a 32-bit register ERd (destination operand) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Instruction Format Mnemonic Operands 1st byte ADD.L ADD.L #xx:32, ERd Rs, ERd 7 0 A A 2nd byte 1 0 erd 3rd byte 4th byte 5th byte 6th byte IMM No. of States 6 2 1 ers 0 erd Notes Rev. 3.00 Dec 13, 2004 page 44 of 258 REJ09B0213-0300 I -- UI -- H U -- N Z V C Section 2 Instruction Descriptions 2.2.2 ADDS ADDS (ADD with Sign extension) Operation Rd + 1 ERd Rd + 2 ERd Rd + 4 ERd Assembly-Language Format ADDS #1, ERd ADDS #2, ERd ADDS #4, ERd Operand Size Longword H: N: Z: V: C: Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- Add Binary Address Data Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction adds the immediate value 1, 2, or 4 to the contents of a 32-bit register ERd. Differing from the ADD instruction, it does not affect the condition code flags. Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Register direct Register direct Mnemonic ADDS ADDS ADDS Operands #1, ERd #2, ERd #4, ERd Instruction Format 1st byte 0 0 0 B B B 2nd byte 0 8 9 0 erd 0 erd 0 erd 3rd byte 4th byte No. of States 2 2 2 Notes Rev. 3.00 Dec 13, 2004 page 45 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.3 ADDX ADDX (ADD with eXtend carry) Operation Rd + (EAs) + C Rd Condition Code Add with Carry Assembly-Language Format ADDX Operand Size Byte H: Set to 1 if there is a carry at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Previous value remains unchanged if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a carry at bit 7; otherwise cleared to 0. Description This instruction adds the source operand and carry flag to the contents of an 8-bit register Rd (destination register) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Mnemonic ADDX ADDX Operands #xx:8, Rd Rs, Rd Instruction Format 1st byte 9 0 rd E rs 2nd byte IMM rd 3rd byte 4th byte No. of States 2 2 Notes Rev. 3.00 Dec 13, 2004 page 46 of 258 REJ09B0213-0300 I -- UI -- H U -- N Z V C Section 2 Instruction Descriptions 2.2.4 (1) AND (B) AND (AND logical) Operation Rd (EAs) Rd Condition Code Logical AND Assembly-Language Format AND.B Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction ANDs the source operand with the contents of an 8-bit register Rd (destination register) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Mnemonic Operands Instruction Format 1st byte 2nd byte 3rd byte 4th byte No. of States Immediate Register direct AND.B AND.B #xx:8, Rd Rs, Rd E 1 rd 6 IMM rs rd I -- UI -- H -- U -- N Z V 0 C -- 2 2 Notes Rev. 3.00 Dec 13, 2004 page 47 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.4 (2) AND (W) AND (AND logical) Operation Rd (EAs) Rd Condition Code Logical AND Assembly-Language Format AND.W Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction ANDs the source operand with the contents of a 16-bit register Rd (destination register) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Mnemonic AND.W AND.W Operands #xx:16, Rd Rs, Rd Instruction Format 1st byte 7 6 9 6 2nd byte 6 rs rd rd 3rd byte IMM 4th byte No. of States 4 2 Notes Rev. 3.00 Dec 13, 2004 page 48 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.4 (3) AND (L) AND (AND logical) Operation ERd (EAs) ERd Condition Code Logical AND Assembly-Language Format AND.L Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction ANDs the source operand with the contents of a 32-bit register ERd (destination register) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Instruction Format Mnemonic Operands 1st byte AND.L AND.L #xx:32, ERd Rs, ERd 7 0 A 1 2nd byte 6 F 0 erd 0 6 6 3rd byte 4th byte 5th byte 6th byte IMM 0 ers 0 erd No. of States 6 4 Notes Rev. 3.00 Dec 13, 2004 page 49 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.5 ANDC ANDC (AND Control register) Operation CCR #IMM CCR Condition Code I UI H U N Z V C Logical AND with CCR Assembly-Language Format ANDC #xx:8, CCR Operand Size Byte I: Stores the corresponding bit of the result. UI: Stores the corresponding bit of the result H: Stores the corresponding bit of the result. U: Stores the corresponding bit of the result N: Stores the corresponding bit of the result. Z: Stores the corresponding bit of the result. V: Stores the corresponding bit of the result. C: Stores the corresponding bit of the result. Description This instruction ANDs the contents of the condition-code register (CCR) with immediate data and stores the result in the condition-code register. No interrupt requests, including NMI, are accepted immediately after execution of this instruction. Operand Format and Number of States Required for Execution Addressing Mode Immediate Mnemonic ANDC Operands #xx:8, CCR Instruction Format 1st byte 0 6 2nd byte IMM 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 50 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.6 BAND BAND (Bit AND) Operation C ( Description This instruction ANDs a specified bit in the destination operand with the carry bit and stores the result in the carry bit. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged. Specified by #xx:3 Bit No. C C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode* Register direct Register indirect Absolute address Mnemonic BAND BAND BAND Operands #xx:3.Rd #xx:3.@ERd #xx:3.@aa:8 Instruction Format 1st byte 7 7 7 6 C E 2nd byte 0 IMM 0 erd abs rd 0 3rd byte 4th byte No. of States 2 6 6 I -- UI -- H -- U -- N -- Z -- V -- C 7 7 6 6 0 IMM 0 IMM 0 0 Note: * The addressing mode is the addressing mode of the destination operand Notes See the corresponding LSI hardware manual for details on the access range for @aa : 8. Rev. 3.00 Dec 13, 2004 page 51 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.7 Bcc Bcc (Branch conditionally) Operation If condition is true, then PC + disp PC else next; Assembly-Language Format Bcc disp Condition field Operand Size -- Description If the condition specified in the condition field (cc) is true, a displacement is added to the program counter (PC) and execution branches to the resulting address. The PC value used in the address calculation is the starting address of the instruction immediately following the Bcc instruction. The displacement is a signed 8-bit or 16-bit value. The branch destination address can be located in the range from -126 to +128 bytes or -32766 to +32768 bytes from the Bcc instruction. Mnemonic BRA (BT) BRn (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Meaning Always (true) Never (false) HIgh Low or Same Carry Clear (High or Same) Carry Set (LOw) Not Equal EQual oVerflow Clear oVerflow Set PLus Minus Greater or Equal Less Than Greater Than Less or Equal cc 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Condition True False CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 Signed/Unsigned* Conditional Branch Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. X > Y (unsigned) X Y (unsigned) X Y (unsigned) X < Y (unsigned) X Y (unsigned or signed) X > Y (unsigned or signed) X Y (signed) X < Y (signed) X > Y (signed) X Y (signed) Note: * If the immediately preceding instruction is a CMP instruction, X is the destination operand and Y is the source operand. Rev. 3.00 Dec 13, 2004 page 52 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Bcc Bcc (Branch conditionally) Operand Format and Number of States Required for Execution Addressing Mnemonic Mode Program-counter BRA (BT) relative Program-counter BRN (BF) relative Program-counter BHI relative Program-counter BLS relative Program-counter Bcc (BHS) relative Program-counter BCS (BLO) relative Program-counter BNE relative Program-counter BEQ relative Program-counter BVC relative Program-counter BVS relative Program-counter BPL relative Program-counter BMI relative Program-counter BGE relative Program-counter BLT relative Program-counter BGT relative Program-counter BLE relative Operands d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 d:8 d:16 1st byte 4 0 5 8 4 1 5 8 4 2 5 8 4 3 5 8 4 4 5 8 4 5 5 8 4 6 5 8 4 7 5 8 4 8 5 8 4 9 5 8 4 A 5 8 4 B 5 8 4 C 5 8 4 D 5 8 4 E 5 8 4 F 5 8 Instruction Format 2nd byte 3rd byte 4th byte disp 0 0 disp disp 1 0 disp disp 2 0 disp disp 3 0 disp disp 4 0 disp disp 5 0 disp disp 6 0 disp disp 7 0 disp disp 8 0 disp disp 9 0 disp disp A 0 disp disp B 0 disp disp C 0 disp disp D 0 disp disp E 0 disp disp F 0 disp No. of States 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 Conditional Branch Notes 1. The branch destination address must be even. 2. In machine language BRA, BRN, BCC, and BCS are identical to BT, BF, BHS, and BLO, respectively. The number of execution states for BRn (BF) is the same as for two NOP instructions. Rev. 3.00 Dec 13, 2004 page 53 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.8 BCLR BCLR (Bit CLeaR) Operation 0 ( I -- UI -- H -- U -- N -- Z -- V -- C -- Bit Clear Assembly-Language Format BCLR #xx:3, H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction clears a specified bit in the destination operand to 0. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register (Rn). The specified bit is not tested. The condition-code flags are not altered. Specified by #xx:3 or Rn Bit No. Available Registers Rd: R0L to R7L, R0H to R7H Rn: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 3.00 Dec 13, 2004 page 54 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions BCLR BCLR (Bit CLeaR) Operand Format and Number of States Required for Execution Addressing Mode* Register direct Register indirect Absolute address Register direct Register indirect Absolute address Mnemonic BCLR BCLR BCLR BCLR BCLR BCLR Operands #xx:3, Rd #xx:3, @ERd #xx:3, @aa:8 Rn, Rd Rn, @ERd Rn, @aa:8 Instruction Format 1st byte 7 7 7 6 7 7 2 D F 2 D F rn 0 erd abs 2nd byte 0 IMM 0 erd abs rd 0 6 6 2 2 rn rn 0 0 rd 0 7 7 2 2 0 IMM 0 IMM 0 0 3rd byte 4th byte No. of States 2 8 8 2 8 8 Bit Clear Note: * The addressing mode is the addressing mode of the destination operand Notes For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 55 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.9 BIAND BIAND (Bit Invert AND) Operation C [ ( Specified by #xx:3 Bit No. Bit Logical AND Condition Code H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation. C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode* Register direct Register indirect Absolute address Mnemonic BIAND BIAND BIAND Operands #xx:3.Rd #xx:3.@ERd #xx:3.@aa:8 Instruction Format 1st byte 7 7 7 6 C E 2nd byte 1 IMM 0 erd abs rd 0 7 7 6 6 1 IMM 1 IMM 0 0 3rd byte 4th byte No. of States 2 6 6 Note: * The addressing mode is the addressing mode of the destination operand Notes For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 56 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N -- Z -- V -- C Section 2 Instruction Descriptions 2.2.10 BILD BILD (Bit Invert LoaD) Operation ( Specified by #xx:3 Bit No. Bit Load Condition Code H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Loaded with the inverse of the specified bit. Invert C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode* Register direct Register indirect Absolute address Mnemonic BILD BILD BILD Operands #xx:3.Rd #xx:3.@ERd #xx:3.@aa:8 Instruction Format 1st byte 7 7 7 7 C E 2nd byte 1 IMM 0 erd abs rd 0 7 7 7 7 1 IMM 1 IMM 0 0 3rd byte 4th byte No. of States 2 6 6 Note: * The addressing mode is the addressing mode of the destination operand Notes For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 57 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N -- Z -- V -- C Section 2 Instruction Descriptions 2.2.11 BIOR BIOR (Bit Invert inclusive OR) Operation C [ ( Specified by #xx:3 Bit No. Bit Logical OR Condition Code H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation. C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode* Register direct Register indirect Absolute address Mnemonic BIOR BIOR BIOR Operands #xx:3.Rd #xx:3.@ERd #xx:3.@aa:8 Instruction Format 1st byte 7 7 7 4 C E 2nd byte 1 IMM 0 erd abs rd 0 7 7 4 4 1 IMM 1 IMM 0 0 3rd byte 4th byte No. of States 2 6 6 Note: * The addressing mode is the addressing mode of the destination operand Notes For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 58 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N -- Z -- V -- C Section 2 Instruction Descriptions 2.2.12 BIST BIST (Bit Invert STore) Operation C ( Specified by #xx:3 Bit No. Bit Store Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. C Invert Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode* Register direct Register indirect Absolute address Mnemonic BIST BIST BIST Operands #xx:3,Rd #xx:3,@ERd #xx:3,@aa:8 Instruction Format 1st byte 6 7 7 7 D F 2nd byte 1 IMM 0 erd abs rd 0 6 6 7 7 1 IMM 1 IMM 0 0 3rd byte 4th byte No. of States 2 8 8 Note: * The addressing mode is the addressing mode of the destination operand Notes For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 59 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.13 BIXOR BIXOR (Bit Invert eXclusive OR) Operation C [ ( Specified by #xx:3 Bit No. Bit Exclusive Logical OR Condition Code H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation. Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode* Register direct Register indirect Absolute address Mnemonic BIXOR BIXOR BIXOR Operands #xx:3,Rd #xx:3,@ERd #xx:3,@aa:8 Instruction Format 1st byte 7 7 7 5 C E 2nd byte 1 IMM 0 erd abs rd 0 7 7 5 5 1 IMM 1 IMM 0 0 3rd byte 4th byte No. of States 2 6 6 Note: * The addressing mode is the addressing mode of the destination operand Notes For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 60 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N -- Z -- V -- C Section 2 Instruction Descriptions 2.2.14 BLD BLD (Bit LoaD) Operation ( Description This instruction loads a specified bit from the destination operand into the carry bit. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged. Specified by #xx:3 Bit No. C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode* Register direct Register indirect Absolute address Mnemonic BLD BLD BLD Operands #xx:3,Rd #xx:3,@ERd #xx:3,@aa:8 Instruction Format 1st byte 7 7 7 7 C E 2nd byte 0 IMM 0 erd abs rd 0 7 7 7 7 0 IMM 0 IMM 0 0 3rd byte 4th byte No. of States 2 6 6 Note: * The addressing mode is the addressing mode of the destination operand Notes For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 61 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N -- Z -- V -- C Section 2 Instruction Descriptions 2.2.15 BNOT BNOT (Bit NOT) Operation ( I -- UI -- H -- U -- N -- Z -- V -- C -- Bit NOT Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction inverts a specified bit in the destination operand. The bit number is specified by 3bit immediate data or by the lower 3 bits of a general register. The specified bit is not tested. The condition code remains unchanged. Specified by #xx:3 or Rn Bit No. Invert Available Registers Rd: R0L to R7L, R0H to R7H Rn: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 3.00 Dec 13, 2004 page 62 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions BNOT BNOT (Bit NOT) Operand Format and Number of States Required for Execution Addressing Mode* Register direct Register indirect Absolute address Register direct Register indirect Absolute address Mnemonic BNOT BNOT BNOT BNOT BNOT BNOT Operands #xx:3, Rd #xx:3, @ERd #xx:3, @aa:8 Rn, Rd Rn, @ERd Rn, @aa:8 Instruction Format 1st byte 7 7 7 6 7 7 1 D F 1 D F rn 0 erd abs 2nd byte 0 IMM 0 erd abs rd 0 6 6 1 1 rn rn 0 0 rd 0 7 7 1 1 0 IMM 0 IMM 0 0 3rd byte 4th byte No. of States 2 8 8 2 8 8 Bit NOT Note: * The addressing mode is the addressing mode of the destination operand Notes For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 63 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.16 BOR BOR (bit inclusive OR) Operation C [( Description This instruction ORs a specified bit in the destination operand with the carry bit and stores the result in the carry bit. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged. Specified by #xx:3 Bit No. C C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode* Register direct Register indirect Absolute address Mnemonic BOR BOR BOR Operands #xx:3,Rd #xx:3,@ERd #xx:3,@aa:8 Instruction Format 1st byte 7 7 7 4 C E 2nd byte 0 IMM 0 erd abs rd 0 7 7 4 4 0 IMM 0 IMM 0 0 3rd byte 4th byte No. of States 2 6 6 Note: * The addressing mode is the addressing mode of the destination operand Notes For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 64 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N -- Z -- V -- C Section 2 Instruction Descriptions 2.2.17 BSET BSET (Bit SET) Operation 1 ( I -- UI -- H -- U -- N -- Z -- V -- C -- Bit Set Description This instruction sets a specified bit in the destination operand to 1. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register. The specified bit is not tested. The condition code flags are not altered. Specified by #xx:3 or Rn Bit No. Available Registers Rd: R0L to R7L, R0H to R7H Rn: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 3.00 Dec 13, 2004 page 65 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions BSET BSET (Bit SET) Operand Format and Number of States Required for Execution Addressing Mode* Register direct Register indirect Absolute address Register direct Register indirect Absolute address Mnemonic BSET BSET BSET BSET BSET BSET Operands #xx:3, Rd #xx:3, @ERd #xx:3, @aa:8 Rn, Rd Rn, @ERd Rn, @aa:8 Instruction Format 1st byte 7 7 7 6 7 7 0 D F 0 D F rn 0 erd abs 2nd byte 0 IMM 0 erd abs rd 0 6 6 0 0 rn rn 0 0 rd 0 7 7 0 0 0 IMM 0 IMM 0 0 3rd byte 4th byte No. of States 2 8 8 2 8 8 Bit Set Note: * The addressing mode is the addressing mode of the destination operand Notes For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 66 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.18 BSR BSR (Branch to SubRoutine) Operation PC @-SP PC + disp PC Assembly-Language Format BSR disp H: N: Z: V: C: Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- Branch to Subroutine Operand Size -- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction branches to a subroutine at a specified address. It pushes the program counter (PC) value onto the stack as a restart address, then adds a specified displacement to the PC value and branches to the resulting address. The PC value pushed onto the stack is the address of the instruction following the BSR instruction. The displacement is a signed 8-bit or 16-bit value, so the possible branching range is -126 to +128 bytes or -32766 to +32768 bytes from the address of the BSR instruction. Operand Format and Number of States Required for Execution Addressing Mode Program-counter relative Instruction Format Mnemonic Operands 1st byte BSR d:8 d:16 5 5 5 C 0 2nd byte 3rd byte disp 0 disp No. of States 4th byte Normal Advanced 6 8 8 10 Rev. 3.00 Dec 13, 2004 page 67 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions BSR BSR (Branch to SubRoutine) Notes The stack structure differs between normal mode and advanced mode. In normal mode only the lower 16 bits of the program counter are pushed on the stack. Reserved Branch to Subroutine PC 23 16 15 87 0 Normal mode PC 23 16 15 87 0 Advanced mode The branch address must be even. Rev. 3.00 Dec 13, 2004 page 68 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.19 BST BST (Bit STore) Operation C ( I -- UI -- H -- U -- N -- Z -- V -- C -- Bit Store Description This instruction stores the carry bit in a specified bit location in the destination operand. The bit number is specified by 3-bit immediate data. Other bits in the destination operand remain unchanged. Specified by #xx:3 Bit No. C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode* Register direct Register indirect Absolute address Mnemonic BST BST BST Operands #xx:3,Rd #xx:3,@ERd #xx:3,@aa:8 Instruction Format 1st byte 6 7 7 7 D F 2nd byte 0 IMM 0 erd abs rd 0 6 6 7 7 0 IMM 0 IMM 0 0 3rd byte 4th byte No. of States 2 8 8 Note: * The addressing mode is the addressing mode of the destination operand Notes For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 69 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.20 BTST BTST (Bit TeST) Operation ( Assembly-Language Format BTST #xx:3, H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Set to 1 if the specified bit is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Description This instruction tests a specified bit in the destination operand and sets or clears the Z flag according to the result. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register. The destination operand remains unchanged. Specified by #xx:3 or Rn Bit No. Available Registers Rd: R0L to R7L, R0H to R7H Rn: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 3.00 Dec 13, 2004 page 70 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N -- Z V -- C -- Section 2 Instruction Descriptions BTST BTST (Bit TeST) Operand Format and Number of States Required for Execution Addressing Mode* Register direct Register indirect Absolute address Register direct Register indirect Absolute address Mnemonic BTST BTST BTST BTST BTST BTST Operands #xx:3, Rd #xx:3, @ERd #xx:3, @aa:8 Rn, Rd Rn, @ERd Rn, @aa:8 Instruction Format 1st byte 7 7 7 6 7 7 3 C E 3 C E rn 0 erd abs 2nd byte 0 IMM 0 erd abs rd 0 6 6 3 3 rn rn 0 0 rd 0 7 7 3 3 0 IMM 0 IMM 0 0 3rd byte 4th byte No. of States 2 6 6 2 6 6 Bit Test Note: * The addressing mode is the addressing mode of the destination operand Notes For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 71 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.21 BXOR BXOR (Bit eXclusive OR) Operation C ( Specified by #xx:3 Bit No. Bit Exclusive Logical OR Condition Code H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Stores the result of the operation. C C Available Registers Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode* Register direct Register indirect Absolute address Mnemonic BXOR BXOR BXOR Operands #xx:3,Rd #xx:3,@ERd #xx:3,@aa:8 Instruction Format 1st byte 7 7 7 5 C E 2nd byte 0 IMM 0 erd abs rd 0 7 7 5 5 0 IMM 0 IMM 0 0 3rd byte 4th byte No. of States 2 6 6 Note: * The addressing mode is the addressing mode of the destination operand Notes For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 72 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N -- Z -- V -- C Section 2 Instruction Descriptions 2.2.22 (1) CMP (B) CMP (CoMPare) Operation Rd - (EAs), set or clear CCR Condition Code Compare Assembly-Language Format CMP.B Operand Size Byte H: Set to 1 if there is a borrow at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 7; otherwise cleared to 0. Description This instruction subtracts the source operand from the contents of an 8-bit register Rd (destination register) and sets or clears the CCR bits according to the result. The destination register contents remain unchanged. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Mnemonic CMP.B CMP.B Operands #xx:8, Rd Rs, Rd Instruction Format 1st byte A 1 rd C rs 2nd byte IMM rd 3rd byte 4th byte No. of States 2 2 Notes Rev. 3.00 Dec 13, 2004 page 73 of 258 REJ09B0213-0300 I -- UI -- H U -- N Z V C Section 2 Instruction Descriptions 2.2.22 (2) CMP (W) CMP (CoMPare) Operation Rd - (EAs), set CCR Condition Code Compare Assembly-Language Format CMP.W Operand Size Word H: Set to 1 if there is a borrow at bit 11; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 15; otherwise cleared to 0. Description This instruction subtracts the source operand from the contents of a 16-bit register Rd (destination register) and sets or clears the CCR bits according to the result. The contents of the 16-bit register Rd remain unchanged. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Mnemonic CMP.W CMP.W Operands #xx:16, Rd Rs, Rd Instruction Format 1st byte 7 1 9 D 2nd byte 2 rs rd rd 3rd byte IMM 4th byte No. of States 4 2 Notes Rev. 3.00 Dec 13, 2004 page 74 of 258 REJ09B0213-0300 I -- UI -- H U -- N Z V C Section 2 Instruction Descriptions 2.2.22 (3) CMP (L) CMP (CoMPare) Operation ERd - (EAs), set CCR Condition Code Compare Assembly-Language Format CMP.L Operand Size Longword I: Previous value remains unchanged. H: Set to 1 if there is a borrow at bit 27; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 31; otherwise cleared to 0. Description This instruction subtracts the source operand from the contents of a 32-bit register ERd (destination register) and sets or clears the CCR bits according to the result. The contents of the 32-bit register ERd remain unchanged. Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Instruction Format Mnemonic Operands 1st byte CMP.L CMP.L #xx:32, ERd ERs, ERd 7 1 A F 2nd byte 2 0 erd 3rd byte 4th byte 5th byte 6th byte IMM No. of States 6 2 1 ers 0 erd Notes Rev. 3.00 Dec 13, 2004 page 75 of 258 REJ09B0213-0300 I -- UI -- H U -- N Z V C Section 2 Instruction Descriptions 2.2.23 DAA DAA (Decimal Adjust Add) Operation Rd (decimal adjust) Rd Condition Code Decimal Adjust Assembly-Language Format DAA Rd Operand Size Byte H: Undetermined (no guaranteed value). N: Set to 1 if the adjusted result is negative; otherwise cleared to 0. Z: Set to 1 if the adjusted result is zero; otherwise cleared to 0. V: Undetermined (no guaranteed value). C: Set to 1 if there is a carry at bit 7; otherwise left unchanged. Description Given that the result of an addition operation performed by an ADD.B or ADDX instruction on 4-bit BCD data is contained in an 8-bit register Rd (destination register) and the carry and halfcarry flags, the DAA instruction adjusts the general register contents by adding H'00, H'06, H'60, or H'66 according to the table below. C Flag before Adjustment 0 0 0 0 0 0 1 1 1 Upper 4 Bits before Adjustment 0 to 9 0 to 8 0 to 9 A to F 9 to F A to F 1 to 2 1 to 2 1 to 3 H Flag before Adjustment 0 0 1 0 0 1 0 0 1 Lower 4 Bits before Adjustment 0 to 9 A to F 0 to 3 0 to 9 A to F 0 to 3 0 to 9 A to F 0 to 3 Value Added (hexadecimal) 00 06 06 60 66 66 60 66 66 C Flag after Adjustment 0 0 0 1 1 1 1 1 1 Available Registers Rd: R0L to R7L, R0H to R7H Rev. 3.00 Dec 13, 2004 page 76 of 258 REJ09B0213-0300 I -- UI -- H * U -- N Z V * C Section 2 Instruction Descriptions DAA DAA (Decimal Adjust Add) Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic DAA Operands Rd Instruction Format 1st byte 0 F 2nd byte 0 rd 3rd byte 4th byte No. of States 2 Decimal Adjust Notes Valid results (8-bit register Rd contents and C, V, Z, N, and H flags) are not assured if this instruction is executed under conditions other than those described above. Rev. 3.00 Dec 13, 2004 page 77 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.24 DAS DAS (Decimal Adjust Subtract) Operation Rd (decimal adjust) Rd Condition Code Decimal Adjust Assembly-Language Format DAS Rd Operand Size Byte H: Undetermined (no guaranteed value). N: Set to 1 if the adjusted result is negative; otherwise cleared to 0. Z: Set to 1 if the adjusted result is zero; otherwise cleared to 0. V: Undetermined (no guaranteed value). C: Previous value remains unchanged. Description Given that the result of a subtraction operation performed by a SUB.B, SUBX.B, or NEG.B instruction on 4-bit BCD data is contained in an 8-bit register Rd (destination register) and the carry and half-carry flags, the DAS instruction adjusts the general register contents by adding H'00, H'FA, H'A0, or H'9A according to the table below. C Flag before Adjustment 0 0 1 1 Upper 4 Bits before Adjustment 0 to 9 0 to 8 7 to F 6 to F H Flag before Adjustment 0 1 0 1 Lower 4 Bits before Adjustment 0 to 9 6 to F 0 to 9 6 to F Value Added (hexadecimal) 00 FA A0 9A C Flag after Adjustment 0 0 1 1 Available Registers Rd: R0L to R7L, R0H to R7H Rev. 3.00 Dec 13, 2004 page 78 of 258 REJ09B0213-0300 I -- UI -- H * U -- N Z V * C -- Section 2 Instruction Descriptions DAS DAS (Decimal Adjust Subtract) Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic DAS Operands Rd Instruction Format 1st byte 1 F 2nd byte 0 rd 3rd byte 4th byte No. of States 2 Decimal Adjust Notes Valid results (8-bit register Rd contents and C, V, Z, N, and H flags) are not assured if this instruction is executed under conditions other than those described above. Rev. 3.00 Dec 13, 2004 page 79 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.25 (1) DEC (B) DEC (DECrement) Operation Rd - 1 Rd Condition Code Decrement Assembly-Language Format DEC.B Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs (the previous value in Rd was H'80); otherwise cleared to 0. C: Previous value remains unchanged. Description This instruction decrements an 8-bit register Rd (destination register) and stores the result in the 8bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic DEC.B Operands Rd Instruction Format 1st byte 1 A 2nd byte 0 rd 3rd byte 4th byte No. of States 2 Notes An overflow is caused by the operation H'80 - 1 H'7F. Rev. 3.00 Dec 13, 2004 page 80 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V C -- Section 2 Instruction Descriptions 2.2.25 (2) DEC (W) DEC (DECrement) Operation Rd - 1 Rd Rd - 2 Rd Condition Code Decrement Assembly-Language Format DEC.W #1, Rd DEC.W #2, Rd Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs (the previous value in Rd was H'8000); otherwise cleared to 0. C: Previous value remains unchanged. Description This instruction subtracts the immediate value 1 or 2 from the contents of a 16-bit register Rd (destination register) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Register direct Mnemonic DEC.W DEC.W Operands #1, Rd #2, Rd Instruction Format 1st byte 1 1 B B 2nd byte 5 D rd rd 3rd byte I 4th byte No. of States 2 2 Notes An overflow is caused by the operations H'8000 - 1 H'7FFF, H'8000 - 2 H'7FFE, and H'8001 - 2 H'7FFF. Rev. 3.00 Dec 13, 2004 page 81 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V C -- Section 2 Instruction Descriptions 2.2.25 (3) DEC (L) DEC (DECrement) Operation ERd - 1 ERd ERd - 2 ERd Assembly-Language Format DEC.L #1, ERd DEC.L #2, ERd Operand Size Longword Condition Code Decrement H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Previous value remains unchanged. Description This instruction subtracts the immediate value 1 or 2 from the contents of a 32-bit register ERd (destination register) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Register direct Mnemonic DEC.L DEC.L Operands #1, ERd #2, ERd Instruction Format 1st byte 1 1 B B 2nd byte 7 F 0 erd 0 erd 3rd byte 4th byte No. of States 2 2 Notes An overflow is caused by the operations H'80000000 - 1 H'7FFFFFFF, H'80000000 - 2 H'7FFFFFFE, and H'80000001 - 2 H'7FFFFFFF. Rev. 3.00 Dec 13, 2004 page 82 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V C -- Section 2 Instruction Descriptions 2.2.26 (1) DIVXS (B) DIVXS (DIVide eXtend as Signed) Operation Rd / Rs Rd Condition Code Divide Signed Assembly-Language Format DIVXS.B Rs, Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the quotient is negative; otherwise cleared to 0. Z: Set to 1 if the divisor is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Description This instruction divides the contents of a 16-bit register Rd (destination register) by the contents of an 8-bit register Rs (source register) and stores the result in the 16-bit register Rd. The division is signed. The operation performed is 16 bits / 8 bits 8-bit quotient and 8-bit remainder. The quotient is placed in the lower 8 bits of Rd. The remainder is placed in the upper 8 bits of Rd. Rd Dividend 16 bits / Rs Divisor 8 bits Rd Remainder 8 bits Quotient 8 bits Valid results are not assured if division by zero is attempted or an overflow occurs. For information on avoiding overflow, see DIVXS Instruction, Zero Divide, and Overflow. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0L to R7L, R0H to R7H Rev. 3.00 Dec 13, 2004 page 83 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V -- C -- Section 2 Instruction Descriptions DIVXS (B) DIVXS (DIVide eXtend as Signed) Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic DIVXS.B Operands Rs, Rd Instruction Format 1st byte 0 1 2nd byte D 0 3rd byte 5 1 4th byte rs rd No. of States 16 Divide Signed Notes The N flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have the same sign. The N flag may therefore be set to 1 when the quotient is zero. Rev. 3.00 Dec 13, 2004 page 84 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.26 (2) DIVXS (W) DIVXS (DIVide eXtend as Signed) Operation ERd / Rs ERd Condition Code Divide Signed Assembly-Language Format DIVXS.W Rs, ERd Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the quotient is negative; otherwise cleared to 0. Z: Set to 1 if the divisor is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Description This instruction divides the contents of a 32-bit register ERd (destination register) by the contents of a 16-bit register Rs (source register) and stores the result in the 32-bit register ERd. The division is signed. The operation performed is 32 bits / 16 bits 16-bit quotient and 16-bit remainder. The quotient is placed in the lower 16 bits (Rd) of the 32-bit register ERd. The remainder is placed in the upper 16 bits (Ed). ERd Dividend 32 bits / Rs Divisor 16 bits ERd Remainder 16 bits Quotient 16 bits Valid results are not assured if division by zero is attempted or an overflow occurs. For information on avoiding overflow, see DIVXS Instruction, Zero Divide, and Overflow. Available Registers ERd: ER0 to ER7 Rs: R0 to R7, E0 to E7 Rev. 3.00 Dec 13, 2004 page 85 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V -- C -- Section 2 Instruction Descriptions DIVXS (W) DIVXS (DIVide eXtend as Signed) Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic DIVXS.W Operands Rs, ERd Instruction Format 1st byte 0 1 2nd byte D 0 3rd byte 5 3 4th byte rs 0 erd No. of States 24 Divide Signed Notes The N flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have the same sign. The N flag may therefore be set to 1 when the quotient is zero. Rev. 3.00 Dec 13, 2004 page 86 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.26 (3) DIVXS DIVXS (DIVide eXtend as Signed) DIVXS instruction, Division by Zero, and Overflow Since the DIVXS instruction does not detect division by zero or overflow, applications should detect and handle division by zero and overflow using techniques similar to those used in the following program. 1. Programming solution for DIVXS.B R0L, R1 Example 1: Convert dividend and divisor to non-negative numbers, then use DIVXU programming solution for zero divide and overflow MOV.B BEQ ANDC BPL NEG.B ORC L1: MOV.W BPL NEG.W XORC L2: MOV.B EXTU.W DIVXU.B MOV.B DIVXU.B MOV.B MOV.B STC BTST BEQ NEG.B L3: BTST BEQ NEG.W L4: RTS ZERODIV: R0L, R0L ZERODIV #AF, CCR L1 R0L #10, CCR R1.R1 L2 R1 #50, CCR R1H, R2L R2 R0L, R2 R2H, R1H R0L, R1 R2L, R2H R1L, R2L CCR, R1L #6, R1L L3 R1H #4, R1L L4 R2 ; Test divisor ; Branch to ZERODIV if R0L = 0 ; Clear CCR user bits (bits 6 and 4) to 0 ; Branch to L1 if N flag = 0 (positive divisor) ; Take 2's complement of R0L to make sign positive ; Set CCR bit 4 to 1 ; Test dividend ; Branch to L2 if N flag = 0 (positive dividend) ; Take 2's complement of R1 to make sign positive ; Invert CCR bits 6 and 4 ; ; ; Use DIVXU.B instruction to divide non-negative dividend ; by positive divisor ; 16 bits / 8 bits quotient (16 bits) and remainder (8 bits) ; (See DIVXU Instruction, Zero Divide, and Overflow) ; ; Copy CCR contents to R1L ; Test CCR bit 6 ; Branch to L3 if bit 6 = 1 ; Take 2's complement of R1H to make sign of remainder negative ; Test CCR bit 4 ; Branch to L4 if bit 4 = 1 ; Take 2's complement of R2 to make sign of quotient negative ; Zero-divide handling routine Divide Signed Rev. 3.00 Dec 13, 2004 page 87 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions DIVXS DIVXS (DIVide eXtend as Signed) This program leaves a 16-bit quotient in R2 and an 8-bit remainder in R1H. R0L R1 Dividend Divisor Divide Signed R1H R2 Remainder Quotient Example 2: Sign extend the 8-bit divisor to 16 bits, sign extend the 16-bit dividend to 32 bits, and then use DIVXS to divide EXTS.W BEQ EXTS.L DIVXS.L RTS ZERODIV: R0 ZERODIV ER1 R0,ER1 This program leaves the 16-bit quotient in R1 and the 8-bit remainder in E1 (in a 16-bit sign extended format). R0L R1 Divisor Dividend ROL ER1 Sign extension Sign extension Divisor Dividend ER1 Remainder Quotient Rev. 3.00 Dec 13, 2004 page 88 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions DIVXS DIVXS (DIVide eXtend as Signed) Divide Signed 2. Programming solution for DIVXS.W R0, ER1 Example: Convert dividend and divisor to non-negative numbers, then use DIVXU programming solution for zero divide and overflow MOV.W BEQ ANDC BPL NEG.W ORC L1: MOV.L BPL NEG.L XORC L2: MOV.W EXTU.L DIVXU.W MOV.W DIVXU.W MOV.W MOV.W STC BTST BEQ NEG.W L3: BTST BEQ NEG.L L4: RTS ZERODIV: R0, R0 ZERODIV #AF, CCR L1 R0 #10, CCR ER1,ER1 L2 ER1 #50,CCR E1, R2 ER2 R0, E2 E2, R1 R0, ER1 R2, E2 R1, R2 CCR, R1L #6, R1L L3 E1 #4, R1L L4 ER2 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Test divisor Branch to ZERODIV if R0 = 0 Clear CCR user bits (bits 6 and 4) to 0 Branch to L1 if N flag = 0 (positive divisor) Take 2's complement of R0 to make sign positive Set CCR bit 4 to 1 Test dividend Branch to L2 if N flag = 0 (positive dividend) Take 2's complement of ER1 to make sign positive Invert CCR bits 6 and 4 Use DIVXU.W instruction to divide non-negative dividend by positive divisor 32 bits / 16 bits quotient (32 bits) and remainder (16 bits) (See DIVXU Instruction, Zero Divide, and Overflow) ; ; ; ; ; ; ; Copy CCR contents to R1L Test CCR bit 6 Branch to L3 if bit 6 = 1 Take 2's complement of E1 to make sign of remainder negative Test CCR bit 4 Branch to L4 if bit 4 = 1 Take 2's complement of ER2 to make sign of quotient negative ; Zero-divide handling routine Rev. 3.00 Dec 13, 2004 page 89 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions DIVXS DIVXS (DIVide eXtend as Signed) This program leaves a 32-bit quotient in ER2 and a 16-bit remainder in E1. R0 ER1 Dividend Divisor Divide Signed E1 ER2 Remainder Quotient The preceding two examples flag the status of the divisor and dividend in the UI and U bits in the CCR, and modify the sign of the quotient and remainder in the unsigned division result of the DIVXU instruction as shown next. UI 0 0 1 1 U 0 1 0 1 Divisor Positive Negative Negative Positive Dividend Positive Positive Negative Negative Remainder Positive Positive Negative Negative Quotient Positive Negative Positive Negative Sign Modification No sign modification Sign of quotient is reversed Sign of remainder is reversed Signs of quotient and remainder are both reversed Rev. 3.00 Dec 13, 2004 page 90 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.27 (1) DIVXU (B) DIVXU (DIVide eXtend as Unsigned) Operation Rd / Rs Rd Condition Code Divide Assembly-Language Format DIVXU.B Rs, Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the divisor is negative; otherwise cleared to 0. Z: Set to 1 if the divisor is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Description This instruction divides the contents of a 16-bit register Rd (destination register) by the contents of an 8-bit register Rs (source register) and stores the result in the 16-bit register Rd. The division is unsigned. The operation performed is 16 bits / 8 bits 8-bit quotient and 8-bit remainder. The quotient is placed in the lower 8 bits of Rd. The remainder is placed in the upper 8 bits of Rd. Rd Dividend 16 bits / Rs Divisor 8 bits Rd Remainder 8 bits Quotient 8 bits Valid results are not assured if division by zero is attempted or an overflow occurs. For information on avoiding overflow, see DIVXU Instruction, Zero Divide, and Overflow. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic DIVXU.B Operands Rs, Rd Instruction Format 1st byte 5 1 2nd byte rs rd 3rd byte 4th byte No. of States 14 Notes Rev. 3.00 Dec 13, 2004 page 91 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V -- C -- Section 2 Instruction Descriptions 2.2.27 (2) DIVXU (W) DIVXU (DIVide eXtend as Unsigned) Operation ERd / Rs ERd Condition Code Divide Assembly-Language Format DIVXU.W Rs, ERd Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the divisor is negative; otherwise cleared to 0. Z: Set to 1 if the divisor is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Description This instruction divides the contents of a 32-bit register ERd (destination register) by the contents of a 16-bit register Rs (source register) and stores the result in the 32-bit register ERd. The division is unsigned. The operation performed is 32 bits / 16 bits 16-bit quotient and 16-bit remainder. The quotient is placed in the lower 16 bits (Rd) of the 32-bit register ERd. The remainder is placed in the upper 8 bits of (Ed). ERd Dividend 32 bits / Rs Divisor 16 bits ERd Remainder 16 bits Quotient 16 bits Valid results are not assured if division by zero is attempted or an overflow occurs. For information on avoiding overflow, see DIVXU Instruction, Zero Divide, and Overflow. Available Registers ERd: ER0 to ER7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic DIVXU.W Operands Rs, ERd Instruction Format 1st byte 5 3 2nd byte rs 0 ERd 3rd byte 4th byte No. of States 22 Notes Rev. 3.00 Dec 13, 2004 page 92 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V -- C -- Section 2 Instruction Descriptions DIVXU DIVXU (DIVide eXtend as Unsigned) DIVXU Instruction, Zero Divide, and Overflow Zero divide and overflow are not detected in the DIVXU instruction. A program like the following can detect zero divisors and avoid overflow. 1. Programming solutions for DIVXU.B R0L, R1 Example 1: Divide upper 8 bits and lower 8 bits of 16-bit dividend separately and obtain 16-bit quotient CMP.B BEQ MOV.B EXTU.W DIVXU.B MOV.B DIVXU.B #0, R0L ZERODIV R1H,R2L R2 (*1). R0L, R2 (*2) ; R0L = 0? (Zero divisor?) ; Branch to ZERODIV if R0L = 0 ; ; Copy upper 8 bits of dividend to R2L and zero-extend to 16 bits Divide ; Divide upper 8 bits of dividend R2H, R1H (*3) ; R2H R1H (store partial remainder in R1H) R0L, R1 (*4) ; Divide lower 8 bits of dividend (including repeated division of upper 8 bits) MOV.B MOV.B RTS ZERODIV: R2L, R2H ; Store upper part of quotient in R2H R1L, R2L (*5) ; Store lower part of quotient in R2L ; Zero-divide handling routine Rev. 3.00 Dec 13, 2004 page 93 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions DIVXU DIVXU (DIVide eXtend as Unsigned) Divide The resulting operation is 16 bits / 8 bits quotient (16 bits) and remainder (8 bits), and no overflow occurs. The 16-bit quotient is stored in R2, the 8-bit remainder in R1H. R0L R1 Divisor Dividend R2 Sign extension Dividend (high) ( *1) R2 Remainder (part) Quotient (high) ( *2) R1 Remainder (part) Dividend (low) ( *3) R1 Remainder Quotient (low) ( *4) R1 R2 Remainder Quotient (low) ( *5) Quotient Rev. 3.00 Dec 13, 2004 page 94 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions DIVXU DIVXU (DIVide eXtend as Unsigned) Divide Example 2: Zero-extend divisor from 8 to 16 bits and dividend from 16 to 32 bits before dividing EXTU.W BEQ EXTU.L EXTU.W RTS ZERODIV: ; Zero-divide handling routine R0 ZERODIV ER1 R0, ER1 ; Zero-extend 8-bit divisor to 16 bits ; Branch to ZERODIV if R0 = 0 ; Zero-extend 16-bit dividend to 32 bits ; Divide using DIVXU.W Instead of 16 bits / 8 bits, the operation performed is 32 bits / 16 bits quotient (16 bits) and remainder (16 bits), and no overflow occurs. The 16-bit quotient is stored in R1 and the 8-bit remainder in the lower 8 bits of E1. The upper 8 bits of E1 are all 0. R0L R1 Divisor Dividend R0L ER1 Sign extension Sign extension Dividend Divisor ER1 Remainder Quotient Rev. 3.00 Dec 13, 2004 page 95 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions DIVXU DIVXU (DIVide eXtend as Unsigned) 2. Programming solution for DIVXU.W R0, ER1 Example 1: Divide upper 16 bits and lower 16 bits of 32-bit dividend separately and obtain 32-bit quotient MOV.W BEQ MOV.W EXTU.L DIVXU.W MOV.W DIVXU.W MOV.W MOV.W RTS ZERODIV: ; Zero-divide handling routine R0, R0 ZERODIV E1,E2 ER2 R0, ER2 E2, E1 R0, ER1 R2, E2 R1, R2 (*5) (*1) (*2) (*3) (*4) ; R0 = 0? (Zero divisor?) ; Branch to ZERODIV if R0 = 0 ; Copy upper 16 bits of dividend to R2 and ; zero-extend to 32 bits ; Divide upper 16 bits of dividend ; E2 E1 (store partial remainder in E1) ; Divide lower 16 bits of dividend (including repeated division of upper 16 bits) Divide ; Store upper part of quotient in E2 ; Store lower part of quotient in R2 The resulting operation is 32 bits / 16 bits quotient (32 bits) and remainder (16 bits), and no overflow occurs. The 32-bit quotient is stored in ER2, the 16-bit remainder in E1. R0 ER1 Dividend Divisor ER2 Sign extension Dividend (high) ( *1) ER2 Remainder (part) Quotient (high) ( *2) ER1 Remainder (part) Dividend (low) ( *3) ER1 Remainder Quotient (low) ( *4) ER1 ER2 Remainder Quotient (low) ( *5) Quotient Rev. 3.00 Dec 13, 2004 page 96 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.28 (1) EEPMOV (B) EEPMOV (MOVe data to EEPROM) Operation if R4L 0 then repeat @ER5+ @ER6+ R4L - 1 R4L until R4L = 0 else next; Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- Block Data Transfer Assembly-Language Format EEPMOV.B Operand Size -- Description H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. This instruction performs a block memory transfer. It moves data from the memory location specified in ER5 to the memory location specified in ER6, increments ER5 and ER6, decrements R4L, and repeats these operations until R4L reaches zero. Execution then proceeds to the next instruction. No interrupts are detected while the block transfer is in progress. When the EEPMOV instruction ends, R4L contains 0, and ER5 and ER6 contain the last transfer address + 1. The data transfer is performed a byte at a time, with R4L indicating the number of bytes to be transferred. The byte symbol in the assembly-language format designates the size of R4L (and limits the maximum number of bytes that can be transferred to 255). Operand Format and Number of States Required for Execution Addressing Mode -- Mnemonic EEPMOV.B Operands Instruction Format 1st byte 7 B 2nd byte 5 C 3rd byte 5 9 4th byte 8 F No. of States 8+4n* Note: * n is the initial value of R4L. Although n bytes of data are transferred, memory is accessed 2(n + 1) times, requiring 4(n + 1) states. (n = 0, 1, 2, ..., 255). Notes This instruction first reads the memory locations indicated by ER5 and ER6, then performs the data transfer. The number of states required for execution differs from the H8/300 CPU. Rev. 3.00 Dec 13, 2004 page 97 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.28 (2) EEPMOV (W) EEPMOV (MOVe data to EEPROM) Operation if R4 0 then repeat @ER5+ @ER6+ R4 - 1 R4 until R4 = 0 else next; Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- Block Data Transfer Assembly-Language Format EEPMOV.W Operand Size -- Description H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. This instruction performs a block memory transfer. It moves data from the memory location specified in ER5 to the memory location specified in ER6, increments ER5 and ER6, decrements R4, and repeats these operations until R4 reaches zero. Execution then proceeds to the next instruction. No interrupts except NMI are detected while the block transfer is in progress. When the EEPMOV instruction ends, R4 contains 0, and ER5 and ER6 contain the last transfer address + 1. The data transfer is performed a byte at a time, with R4 indicating the number of bytes to be transferred. The word symbol in the assembly-language format designates the size of R4 (allowing a maximum 65535 bytes to be transferred). Operand Format and Number of States Required for Execution Addressing Mode -- Mnemonic EEPMOV.W Operands Instruction Format 1st byte 7 B 2nd byte D 4 3rd byte 5 9 4th byte 8 F No. of States 8+4n Note: n is the initial value of R4. Although n bytes of data are transferred, memory is accessed 2(n + 1) times, requiring 4(n + 1) states. (n = 0, 1, 2, ..., 65535). Notes This instruction first reads memory at the addresses indicated by ER5 and ER6, then carries out the block data transfer. Rev. 3.00 Dec 13, 2004 page 98 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions EEPMOV (W) EEPMOV (MOVe data to EEPROM) EEPMOV.W Instruction and NMI Interrupt If an NMI request occurs while the EEPMOV.W instruction is being executed, NMI interrupt exception handling is carried out at the end of the current read-write cycle. Register contents are then as follows: ER5: address of the next byte to be transferred ER6: destination address of the next byte R4: number of bytes remaining to be transferred The program counter value pushed on the stack in NMI interrupt exception handling is the address of the next instruction after the EEPMOV.W instruction. Programs should be coded as follows to allow for NMI interrupts during execution of the EEPMOV.W instruction. Example: L1: EEPMOV.W MOV.W BNE R4, R4 L1 Block Data Transfer During execution of the EEPMOV.B instruction no interrupts are accepted, including NMI. Rev. 3.00 Dec 13, 2004 page 99 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.29 (1) EXTS (W) EXTS (EXTend as Signed) Operation ( Assembly-Language Format EXTS.W Rd Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction copies the sign of the lower 8 bits in a 16-bit register Rd in the upward direction (copies Rd bit 7 to bits 15 to 8) to extend the data to signed word data. Rd Don't care 8 bits 8 bits Sign bit Sign extension 8 bits 8 bits Rd Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic EXTS.W Operands Rd Instruction Format 1st byte 1 7 2nd byte D rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 100 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.29 (2) EXTS (L) EXTS (EXTend as Signed) Operation ( Operand Size Longword I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction copies the sign of the lower 16 bits (general register Rd) in a 32-bit register ERd in the upward direction (copies ERd bit 15 to bits 31 to 16) to extend the data to signed longword data. ERd Don't care 16 bits 16 bits Sign bit ERd Sign extension 16 bits 16 bits Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic EXTS.L Operands ERd Instruction Format 1st byte 1 7 2nd byte F 0 erd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 101 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.30 (1) EXTU (W) EXTU (EXTend as Unsigned) Operation 0 ( Operand Size Word H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction extends the lower 8 bits in a 16-bit register Rd to word data by padding with zeros. That is, it clears the upper 8 bits of Rd (bits 15 to 8) to 0. Rd Don't care 8 bits 8 bits Zero extension 8 bits 8 bits Rd Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic EXTU.W Operands Rd Instruction Format 1st byte 1 7 2nd byte 5 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 102 of 258 REJ09B0213-0300 I -- UI -- HU ---- N 0 Z V 0 C -- Section 2 Instruction Descriptions 2.2.30 (2) EXTU (L) EXTU (EXTend as Unsigned) Operation 0 ( Operand Size Longword H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction extends the lower 16 bits (general register Rd) in a 32-bit register ERd to longword data by padding with zeros. That is, it clears the upper 16 bits of ERd (bits 31 to 16) to 0. ERd Don't care 16 bits 16 bits ERd Zero extension 16 bits 16 bits Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic EXTU.L Operands ERd Instruction Format 1st byte 1 7 2nd byte 7 0 erd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 103 of 258 REJ09B0213-0300 I -- UI -- HU ---- N 0 Z V 0 C -- Section 2 Instruction Descriptions 2.2.31 (1) INC (B) INC (INCrement) Operation Rd + 1 Rd Condition Code Increment Assembly-Language Format INC.B Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Previous value remains unchanged. Description This instruction increments an 8-bit register Rd (destination register) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic INC.B Operands Rd Instruction Format 1st byte 0 A 2nd byte 0 rd 3rd byte 4th byte No. of States 2 Notes An overflow is caused by the operation H'7F + 1 H'80. Rev. 3.00 Dec 13, 2004 page 104 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V C -- Section 2 Instruction Descriptions 2.2.31 (2) INC (W) INC (INCrement) Operation Rd + 1 Rd Rd + 2 Rd Assembly-Language Format INC.W #1, Rd INC.W #2, Rd Operand Size Word Condition Code Increment H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Previous value remains unchanged. Description This instruction adds the immediate value 1 or 2 to the contents of a 16-bit register Rd (destination register) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Register direct Mnemonic INC.W INC.W Operands #1, Rd #2, Rd Instruction Format 1st byte 0 0 B B 2nd byte 5 D rd rd 3rd byte 4th byte No. of States 2 2 Notes An overflow is caused by the operations H'7FFF + 1 H'8000, H'7FFF + 2 H'8001, and H'7FFE + 2 H'8000. Rev. 3.00 Dec 13, 2004 page 105 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V C -- Section 2 Instruction Descriptions 2.2.31 (3) INC (L) INC (INCrement) Operation ERd + 1 ERd ERd + 2 ERd Assembly-Language Format INC.L #1, ERd INC.L #2, ERd Operand Size Longword Condition Code Increment H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Previous value remains unchanged. Description This instruction adds the immediate value 1 or 2 to the contents of a 32-bit register ERd (destination register) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Register direct Mnemonic INC.L INC.L Operands #1, ERd #2, ERd Instruction Format 1st byte 0 0 B B 2nd byte 7 F 0 erd 0 erd 3rd byte 4th byte No. of States 2 2 Notes An overflow is caused by the operations H'7FFFFFFF + 1 H'80000000, H'7FFFFFFF + 2 H'80000001, and H'7FFFFFFE + 2 H'80000000. Rev. 3.00 Dec 13, 2004 page 106 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V C -- Section 2 Instruction Descriptions 2.2.32 JMP JMP (JuMP) Operation Effective address PC Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- Unconditional Branch Assembly-Language Format JMP Operand Size -- H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction branches unconditionally to a specified address Available Registers ERn: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register indirect Absolute address Memory indirect Instruction Format Mnemonic JMP JMP JMP Operands 1st byte @ERn @aa:24 @@aa:8 5 5 5 9 A B abs 2nd byte 0 ern 0 abs 8 3rd byte 4th byte Normal 4 6 10 Advanced No. of States Notes The structure of the branch address and the number of states required for execution differ between normal mode and advanced mode. The branch address must be even. Rev. 3.00 Dec 13, 2004 page 107 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.33 JSR JSR (Jump to SubRoutine) Operation PC @-SP Effective address PC Assembly-Language Format JSR I -- UI -- H -- U -- N -- Z -- V -- C -- Jump to Subroutine Operand Size -- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction pushes the program counter on the stack as a return address, then branches to a specified effective address. The program counter value pushed on the stack is the address of the instruction following the JSR instruction. Available Registers ERn: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register indirect Absolute address Memory indirect Instruction Format Mnemonic JSR JSR JSR Operands 1st byte @ERn @aa:24 @@aa:8 5 5 5 D E F abs 2nd byte 0 ern 0 abs 3rd byte 4th byte Normal 6 8 8 Advanced 8 10 12 No. of States Rev. 3.00 Dec 13, 2004 page 108 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions JSR JSR (Jump to SubRoutine) Notes Note that the structures of the stack and branch addresses differ between normal and advanced mode. Only the lower 16 bits of the PC are saved in normal mode. The branch address must be even. Reserved Jump to Subroutine PC 23 16 15 87 0 Normal mode PC 23 16 15 87 0 Advanced mode Rev. 3.00 Dec 13, 2004 page 109 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.34 (1) LDC (B) LDC (LoaD to Control register) Operation (EAs) CCR Condition Code I UI H U N Z V C Load CCR Assembly-Language Format LDC.B Operand Size Byte I: Loaded from the corresponding bit in the source operand. H: Loaded from the corresponding bit in the source operand. N: Loaded from the corresponding bit in the source operand. Z: Loaded from the corresponding bit in the source operand. V: Loaded from the corresponding bit in the source operand. C: Loaded from the corresponding bit in the source operand. Description This instruction loads the source operand into the CCR. Note that no interrupts, even NMI interrupts, will be accepted at the point that this instruction completes. Available Registers Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Mnemonic LDC.B LDC.B Operands #xx:8, CCR Rs, CCR Instruction Format 1st byte 0 0 7 3 0 2nd byte IMM rs 3rd byte 4th byte No. of States 2 2 Notes Rev. 3.00 Dec 13, 2004 page 110 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.34 (2) LDC (W) LDC (LoaD to Control register) Operation (EAs) CCR Condition Code I UI H U N Z V C Load CCR Assembly-Language Format LDC.W Operand Size Word I: Loaded from the corresponding bit in the source operand. H: Loaded from the corresponding bit in the source operand. N: Loaded from the corresponding bit in the source operand. Z: Loaded from the corresponding bit in the source operand. V: Loaded from the corresponding bit in the source operand. C: Loaded from the corresponding bit in the source operand. Description This instruction loads the source operand contents into the condition-code register (CCR). Although CCR is a byte register, the source operand is word size. The contents of the even address are loaded into CCR. No interrupt requests, including NMI, are accepted immediately after execution of this instruction. Available Registers ERs: ER0 to ER7 Rev. 3.00 Dec 13, 2004 page 111 of 258 REJ09B0213-0300 Operand Format and Number of States Required for Execution Instruction Format 1st byte 0 1 6 4 0 6 9 0 ers 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte No. of States LDC (W) Addressing Mode Mnemonic Operands Register indirect LDC.W @ERs,CCR LDC.W disp @(d:16,ERs),CCR 0 1 4 0 6 F 0 ers 0 8 Register indirect with displacement 0 6 B 2 0 0 0 disp 1 4 0 7 8 0 ers 0 12 Section 2 Instruction Descriptions LDC (LoaD to Control register) LDC.W @(d:24,ERs),CCR Register indirect with post-increment 0 1 4 0 6 D 0 ers 0 0 0 1 4 0 6 B 0 abs LDC.W @ERs+,CCR 8 Rev. 3.00 Dec 13, 2004 page 112 of 258 REJ09B0213-0300 8 0 2 abs 0 0 1 4 0 6 B 0 10 LDC.W @aa:16,CCR Absolute address LDC.W @aa:24,CCR Notes Load CCR Section 2 Instruction Descriptions 2.2.35 (1) MOV (B) MOV (MOVe data) Operation Rs Rd Condition Code Move Assembly-Language Format MOV.B Rs, Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers one byte of data from an 8-bit register Rs to an 8-bit register Rd, tests the transferred data, and sets condition-code flags according to the result. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic MOV.B Operands Rs, Rd Instruction Format 1st byte 0 C 2nd byte rs rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 113 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.35 (2) MOV (W) MOV (MOVe data) Operation Rs Rd Condition Code Move Assembly-Language Format MOV.W Rs, Rd Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers one word of data from a 16-bit register Rs to a 16-bit register Rd, tests the transferred data, and sets condition-code flags according to the result. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic MOV.W Operands Rs, Rd Instruction Format 1st byte 0 D 2nd byte rs rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 114 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.35 (3) MOV (L) MOV (MOVe data) Operation ERs ERd Condition Code Move Assembly-Language Format MOV.L ERs, ERd Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers one longword of data from a 32-bit register ERs to a 32-bit register ERd, tests the transferred data, and sets condition-code flags according to the result. Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic MOV.L Operands ERs, ERd Instruction Format 1st byte 0 F 2nd byte 1 ers 0 erd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 115 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.35 (4) MOV (B) MOV (MOVe data) Operation (EAs) Rd Condition Code Move Assembly-Language Format MOV.B Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers the source operand contents to an 8-bit register Rs, tests the transferred data, and sets condition-code flags according to the result. Available Registers Rd: R0L to R7L, R0H to R7H ERs: ER0 to ER7 Rev. 3.00 Dec 13, 2004 page 116 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Operand Format and Number of States Required for Execution Instruction Format 1st byte F IMM rd 2 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte No. of States MOV (B) Addressing Mode Mnemonic Operands MOV (MOVe data) Immediate MOV.B #xx:8,Rd Register indirect 6 8 rd 4 0 ers MOV.B @ERs,Rd MOV.B disp @(d:16,ERs),Rd 6 E rd 6 0 ers Register indirect with displacement 7 6 A 2 rd 0 0 disp 8 0 ers 0 10 MOV.B @(d:24,ERs),Rd Register indirect with post-increment 6 C 0 ers rd 2 abs rd MOV.B @ERs+,Rd 6 MOV.B @aa:8,Rd 4 Absolute address 6 0 rd A abs MOV.B @aa:16,Rd 6 MOV.B abs @aa:24,Rd 2 0 rd 0 6 A 8 Notes The MOV.B @ER7+, Rd instruction should never be used, because it leaves an odd value in the stack pointer (ER7). For details refer to section 3.3.2, Exception Processing, or to the hardware manual. For the @aa:8 access range, refer to the relevant microcontroller hardware manual. Section 2 Instruction Descriptions Move Rev. 3.00 Dec 13, 2004 page 117 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.35 (5) MOV (W) MOV (MOVe data) Operation (EAs) Rd Condition Code Move Assembly-Language Format MOV.W Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers the source operand contents to a 16-bit register Rd, tests the transferred data, and sets condition-code flags according to the result. Available Registers Rd: R0 to R7, E0 to E7 ERs: ER0 to ER7 Rev. 3.00 Dec 13, 2004 page 118 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Operand Format and Number of States Required for Execution Instruction Format Mnemonic 1st byte MOV.W IMM #xx:16,Rd 7 9 0 rd 4 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte Operands No. of States MOV (W) Addressing Mode MOV (MOVe data) Immediate Register indirect MOV.W 6 @ERs,Rd 9 0 ers rd 4 MOV.W disp @(d:16,ERs),Rd 6 0 ers F rd 6 Register indirect with displacement MOV.W rd 0 0 @(d:24,ERs),Rd 2 7 0 ers 8 0 6 B disp 10 Register indirect with post-increment MOV.W @ERs+,Rd 0 ers 6 D rd MOV.W @aa:16,Rd 6 0 abs B rd 6 6 Absolute address MOV.W @aa:24,Rd 6 2 B rd 0 0 abs 8 Notes 1. The source operand Section 2 Instruction Descriptions Move Rev. 3.00 Dec 13, 2004 page 119 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.35 (6) MOV (L) MOV (MOVe data) Operation (EAs) ERd Condition Code Move Assembly-Language Format MOV.L Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers the source operand contents to a specified 32-bit register (ERd), tests the transferred data, and sets condition-code flags according to the result. The first memory word located at the effective address is stored in extended register Ed. The next word is stored in general register Rd. MSB EA LSB ERd Ed RdH RdL Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Rev. 3.00 Dec 13, 2004 page 120 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Operand Format and Number of States Required for Execution Instruction Format 1st byte 7 IMM A 0 ers 0 6 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte No. of States MOV (L) Addressing Mode Mnemonic Operands MOV (MOVe data) Immediate MOV.L #xx:32,Rd Register indirect 0 9 1 0 ers 0 erd 0 6 0 MOV.L @ERs,ERd 8 Register indirect with displacement 0 8 0 ers 0 B 2 0 erd 0 0 6 1 7 0 0 MOV.L @(d:16,ERs),ERd 0 F 0 ers 0 erd 1 6 disp 0 0 10 MOV.L @(d:24,ERs),ERd disp 14 Register indirect with post-increment 0 6 D 0 ers 0 erd 1 0 0 0 6 B 0 erd abs 1 0 0 0 MOV.L @ERs+,ERd 10 MOV.L @aa:16,ERd 10 Absolute address 0 6 0 erd 0 0 B 1 0 0 2 abs 12 MOV.L @aa:24,ERd Notes 1. The source operand Section 2 Instruction Descriptions Move Rev. 3.00 Dec 13, 2004 page 121 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.35 (7) MOV (B) MOV (MOVe data) Operation Rs (EAd) Condition Code Move Assembly-Language Format MOV.B Rs, Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers the contents of an 8-bit register Rs (source operand) to a destination location, tests the transferred data, and sets condition-code flags according to the result. Available Registers Rs: R0L to R7L, R0H to R7H ERd: ER0 to ER7 Rev. 3.00 Dec 13, 2004 page 122 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Operand Format and Number of States Required for Execution Instruction Format 1st byte 6 8 1 erd rs 4 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte No. of States MOV (B) Addressing Mode Mnemonic Operands MOV (MOVe data) Register indirect MOV.B Rs,@ERd MOV.B 6 disp Rs,@(d:16,ERd) E 1 erd rs 6 Register indirect with displacement 7 6 A A rs 0 disp 0 8 0 erd 0 10 MOV.B Rs,@(d:24,ERd) Register indirect with pre-decrement 6 C 1 erd rs 3 abs rs MOV.B Rs,@-ERd 6 MOV.B Rs,@aa:8 4 Absolute address 6 8 rs A abs MOV.B Rs,@aa:16 6 MOV.B abs Rs,@aa:24 6 A 0 rs 0 A 8 Notes 1. The MOV.B Rs, @-ER7 instruction should never be used, because it leaves an odd value in the stack pointer (ER7). For details refer to section 3.3.2, Exception Processing, or to the hardware manual. 2. Execution of MOV.B RnL, @-ERn or MOV.B RnH, @-ERn first decrements ERn by one, then transfers the designated part (RnL or RnH) of the resulting ERn value. Section 2 Instruction Descriptions Move Rev. 3.00 Dec 13, 2004 page 123 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.35 (8) MOV (W) MOV (MOVe data) Operation Rs (EAd) Condition Code Move Assembly-Language Format MOV.W Rs, Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers the contents of a 16-bit register Rs (source operand) to a destination location, tests the transferred data, and sets condition-code flags according to the result. Available Registers Rs: R0 to R7, E0 to E7 ERd: ER0 to ER7 Rev. 3.00 Dec 13, 2004 page 124 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Operand Format and Number of States Required for Execution Instruction Format Mnemonic 1st byte MOV.W Rs,@ERd 6 9 1 erd rs 4 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte Operands No. of States MOV (W) Addressing Mode MOV (MOVe data) Register indirect MOV.W Rs,@(d:16,ERd) disp 6 F 1 erd rs 6 Register indirect with displacement MOV.W rs 0 disp 0 Rs,@(d:24,ERd) 6 B A 7 8 0 erd 0 10 Register indirect with post-increment MOV.W Rs,@-ERd 6 D 1 erd rs MOV.W Rs,@aa:16 8 rs 6 B abs 6 6 Absolute address MOV.W Rs,@aa:24 A 0 rs 0 6 B abs 8 Notes 1. The destination operand Section 2 Instruction Descriptions Move Rev. 3.00 Dec 13, 2004 page 125 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.35 (9) MOV (L) MOV (MOVe data) Operation ERs (EAd) Condition Code Move Assembly-Language Format MOV.L ERs, Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers the contents of a 32-bit register ERs (source operand) to a destination location, tests the transferred data, and sets condition-code flags according to the result. The extended register (Es) contents are stored at the first word indicated by the effective address. The general register (Rs) contents are stored at the next word. MSB EA LSB ERs Es RsH RsL Available Registers ERs: ER0 to ER7 ERd: ER0 to ER7 Rev. 3.00 Dec 13, 2004 page 126 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Operand Format and Number of States Required for Execution Instruction Format 1st byte 0 1 0 0 6 9 1 erd 0 ers 8 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte No. of States MOV (L) Addressing Mode Mnemonic Operands MOV (MOVe data) Register indirect MOV.L ERs,@ERd MOV.L disp ERs,@(d:16,ERd) 0 1 0 0 6 F 1 erd 0 ers 10 Register indirect with displacement 0 6 B A 0 ers 0 0 disp 1 0 0 7 8 1 erd 0 14 MOV.L ERs,@(d:24,ERd) Register indirect with pre-decrement 0 1 0 0 6 D 1 erd 0 ers 0 8 0 ers 1 0 0 6 B abs MOV.L ERs,@-ERd 10 MOV.L ERs,@aa:16 10 Absolute address 0 A 0 ers 0 0 1 0 0 6 B abs 12 MOV.L ERs,@aa:24 Notes 1. The destination operand Section 2 Instruction Descriptions Move Rev. 3.00 Dec 13, 2004 page 127 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.36 MOVFPE MOVFPE (MOVe From Peripheral with E clock) Operation (EAs) Rd Synchronized with E clock Assembly-Language Format MOVFPE @aa:16, Rd Operand Size Byte Condition Code Move Data with E Clock H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers memory contents specified by a 16-bit absolute address to a general register Rd in synchronization with an E clock, tests the transferred data, and sets condition-code flags according to the result. Note: Avoid using this instruction in microcontrollers not having an E clock output pin, or in single-chip mode. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Absolute address Mnemonic MOVFPE Operands @aa:16, Rd Instruction Format 1st byte 6 A 2nd byte 4 rd 3rd byte abs 4th byte No. of States * Notes 1. This instruction cannot be used with addressing modes other than the above, and cannot transfer word data or longword data. 2. Data transfer by this instruction requires 9 to 16 states, so the execution time is variable. For details, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 128 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.37 MOVTPE MOVTPE (MOVe To Peripheral with E clock) Operation Rs (EAd) Synchronized with E clock Assembly-Language Format MOVTPE Rs, @aa:16 Condition Code Move Data with E Clock Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction transfers the contents of a general register Rs (source operand) to a destination location specified by a 16-bit absolute address in synchronization with an E clock, tests the transferred data, and sets condition-code flags according to the result. Note: Avoid using this instruction in microcontrollers not having an E clock output pin, or in single-chip mode. Available Registers Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Absolute address Mnemonic MOVTPE Operands Rs, @aa:16 Instruction Format 1st byte 6 A 2nd byte C rs 3rd byte abs 4th byte No. of States * Notes 1. This instruction cannot be used with addressing modes other than the above, and cannot transfer word data or longword data. 2. Data transfer by this instruction requires 9 to 16 states, so the execution time is variable. For details, refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 129 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.38 (1) MULXS (B) MULXS (MULtiply eXtend as Signed) Operation Rd x Rs Rd Condition Code Multiply Signed Assembly-Language Format MULXS.B Rs, Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Description This instruction multiplies the lower 8 bits of a 16-bit register Rd (destination operand) by the contents of an 8-bit register Rs (source operand) as signed data and stores the result in the 16-bit register Rd. If Rd is a general register, Rs can be the upper part (RdH) or lower part (RdL) of Rd. The operation performed is 8-bit x 8-bit 16-bit signed multiplication. Rd Don't care Multiplicand 8 bits x Rs Multiplier 8 bits Rd Product 16 bits Available Registers Rd: R0 to R7, E0 to E7 Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic MULXS.B Operands Rs, Rd Instruction Format 1st byte 0 1 2nd byte C 0 3rd byte 5 0 4th byte rs rd No. of States 16 Notes Rev. 3.00 Dec 13, 2004 page 130 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N Z V -- C -- Section 2 Instruction Descriptions 2.2.38 (2) MULXS (W) MULXS (MULtiply eXtend as Signed) Operation ERd x Rs ERd Condition Code Multiply Signed Assembly-Language Format MULXS.W Rs, ERd Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged. Description This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination operand) by the contents of a 16-bit register Rs (source operand) as signed data and stores the result in the 32-bit register ERd. Rs can be the upper part (Ed) or lower part (Rd) of ERd. The operation performed is 16-bit x 16-bit 32-bit signed multiplication. ERd Don't care Multiplicand 16 bits x Rs Multiplier 16 bits ERd Product 32 bits Available Registers ERd: ER0 to ER7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic MULXS.W Operands Rs, ERd Instruction Format 1st byte 0 1 2nd byte C 0 3rd byte 5 2 4th byte rs 0 erd No. of States 24 Notes Rev. 3.00 Dec 13, 2004 page 131 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N Z V -- C -- Section 2 Instruction Descriptions 2.2.39 (1) MULXU (B) MULXU (MULtiply eXtend as Unsigned) Operation Rd x Rs Rd Assembly-Language Format MULXU.B Rs, Rd Operand Size Byte Description This instruction multiplies the lower 8 bits of a 16-bit register Rd (destination operand) by the contents of an 8-bit register Rs (source operand) and stores the result in the 16-bit register Rd. If Rd is a general register, Rs can be the upper part (RdH) or lower part (RdL) of Rd. The operation performed is 8-bit x 8-bit 16-bit multiplication. Rd Don't care Multiplicand 8 bits x Rs Multiplier 8 bits Rd Product 16 bits Multiply Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic MULXU.B Operands Rs, Rd Instruction Format 1st byte 5 0 2nd byte rs rd 3rd byte 4th byte No. of States 14 Notes Rev. 3.00 Dec 13, 2004 page 132 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.39 (2) MULXU (W) MULXU (MULtiply eXtend as Unsigned) Operation ERd x Rs ERd Assembly-Language Format MULXU.W Rs, ERd Operand Size Word Description This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination operand) by the contents of a 16-bit register Rs (source operand) and stores the result in the 32-bit register ERd. Rs can be the upper part (Ed) or lower part (Rd) of ERd. The operation performed is 16-bit x 16-bit 32-bit multiplication. ERd Don't care Multiplicand 16 bits x Rs Multiplier 16 bits ERd Product 32 bits Multiply Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Available Registers ERd: ER0 to ER7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic MULXU.W Operands Rs, ERd Instruction Format 1st byte 5 2 2nd byte rs 0 erd 3rd byte 4th byte No. of States 22 Notes Rev. 3.00 Dec 13, 2004 page 133 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.40 (1) NEG (B) NEG (NEGate) Operation 0 - Rd Rd Condition Code Negate Binary Signed Assembly-Language Format NEG.B Rd Operand Size Byte H: Set to 1 if there is a borrow at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 7; otherwise cleared to 0. Description This instruction takes the two's complement of the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd (subtracting the register contents from H'00). If the original contents of Rd was H'80, however, the result remains H'80. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic NEG.B Operands Rd Instruction Format 1st byte 1 7 2nd byte 8 rd 3rd byte 4th byte No. of States 2 Notes An overflow occurs if the previous contents of Rd was H'80. Rev. 3.00 Dec 13, 2004 page 134 of 258 REJ09B0213-0300 I -- UI -- H U -- N Z V C Section 2 Instruction Descriptions 2.2.40 (2) NEG (W) NEG (NEGate) Operation 0 - Rd Rd Condition Code Negate Binary Signed Assembly-Language Format NEG.W Rd Operand Size Word H: Set to 1 if there is a borrow at bit 11; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 15; otherwise cleared to 0. Description This instruction takes the two's complement of the contents of a 16-bit register Rd (destination operand) and stores the result in the 16-bit register Rd (subtracting the register contents from H'0000). If the original contents of Rd was H'8000, however, the result remains H'8000. Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic NEG.W Operands Rd Instruction Format 1st byte 1 7 2nd byte 9 rd 3rd byte 4th byte No. of States 2 Notes An overflow occurs if the previous contents of Rd was H'8000. Rev. 3.00 Dec 13, 2004 page 135 of 258 REJ09B0213-0300 I -- UI -- H U -- N Z V C Section 2 Instruction Descriptions 2.2.40 (3) NEG (L) NEG (NEGate) Operation 0 - ERd ERd Condition Code Negate Binary Signed Assembly-Language Format NEG.L ERd Operand Size Longword H: Set to 1 if there is a borrow at bit 27; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 31; otherwise cleared to 0. Description This instruction takes the two's complement of the contents of a 32-bit register ERd (destination operand) and stores the result in the 32-bit register ERd (subtracting the register contents from H'00000000). If the original contents of ERd was H'80000000, however, the result remains H'80000000. Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic NEG.L Operands ERd Instruction Format 1st byte 1 7 2nd byte B 0 erd 3rd byte 4th byte No. of States 2 Notes An overflow occurs if the previous contents of ERd was H'80000000. Rev. 3.00 Dec 13, 2004 page 136 of 258 REJ09B0213-0300 I -- UI -- H U -- N Z V C Section 2 Instruction Descriptions 2.2.41 NOP NOP (No OPeration) Operation PC + 2 PC Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- No Operation Assembly-Language Format NOP Operand Size -- H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction only increments the program counter, causing the next instruction to be executed. The internal state of the CPU does not change. Available Registers -- Operand Format and Number of States Required for Execution Addressing Mode -- Mnemonic NOP Operands Instruction Format 1st byte 0 0 2nd byte 0 0 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 137 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.42 (1) NOT (B) NOT (NOT = logical complement) Operation Rd Rd Condition Code Logical Complement Assembly-Language Format NOT.B Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction takes the one's complement of the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic NOT.B Operands Rd Instruction Format 1st byte 1 7 2nd byte 0 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 138 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.42 (2) NOT (W) NOT (NOT = logical complement) Operation Rd Rd Condition Code Logical Complement Assembly-Language Format NOT.W Rd Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero (the previous Rd value was H'FFFF); otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction takes the one's complement of the contents of a 16-bit register Rd (destination operand) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic NOT.W Operands Rd Instruction Format 1st byte 1 7 2nd byte 1 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 139 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.42 (3) NOT (L) NOT (NOT = logical complement) Operation ERd ERd Condition Code Logical Complement Assembly-Language Format NOT.L ERd Operand Size Longword I: Previous value remains unchanged. H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction takes the one's complement of the contents of a 32-bit register ERd (destination operand) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic NOT.L Operands ERd Instruction Format 1st byte 1 7 2nd byte 3 0 erd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 140 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.43 (1) OR (B) OR (inclusive OR logical) Operation Rd (EAs) Rd Condition Code Logical OR Assembly-Language Format OR.B Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction ORs the source operand with the contents of an 8-bit register Rd (destination register) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Mnemonic OR.B OR.B Operands #xx:8, Rd Rs, Rd Instruction Format 1st byte C 1 rd 4 rs 2nd byte IMM rd 3rd byte 4th byte No. of States 2 2 Notes Rev. 3.00 Dec 13, 2004 page 141 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.43 (2) OR (W) OR (inclusive OR logical) Operation Rd (EAs) Rd Condition Code Logical OR Assembly-Language Format OR.W Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction ORs the source operand with the contents of a 16-bit register Rd (destination register) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Mnemonic OR.W OR.W Operands #xx:16, Rd Rs, Rd Instruction Format 1st byte 7 6 9 4 2nd byte 4 rs rd rd 3rd byte IMM 4th byte No. of States 4 2 Notes Rev. 3.00 Dec 13, 2004 page 142 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.43 (3) OR (L) OR (inclusive OR logical) Operation ERd (EAs) ERd Condition Code Logical OR Assembly-Language Format OR.L Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction ORs the source operand with the contents of a 32-bit register ERd (destination register) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Instruction Format Mnemonic Operands 1st byte OR.L OR.L #xx:32,ERd ERs, ERd 7 0 A 1 2nd byte 4 F 0 erd 0 6 4 3rd byte 4th byte 5th byte 6th byte IMM 0 ers 0 erd No. of States 6 4 Notes Rev. 3.00 Dec 13, 2004 page 143 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.44 ORC ORC (inclusive OR Control register) Operation CCR #IMM CCR Condition Code I UI H U N Z V C Logical OR with CCR Assembly-Language Format ORC #xx:8, CCR Operand Size Byte I: Stores the corresponding bit of the result. UI: Stores the corresponding bit of the result. H: Stores the corresponding bit of the result. U: Stores the corresponding bit of the result. N: Stores the corresponding bit of the result. Z: Stores the corresponding bit of the result. V: Stores the corresponding bit of the result. C: Stores the corresponding bit of the result. Description This instruction ORs the contents of the condition-code register (CCR) with immediate data and stores the result in the condition-code register. No interrupt requests, including NMI, are accepted immediately after execution of this instruction. Operand Format and Number of States Required for Execution Addressing Mode Immediate Mnemonic ORC Operands #xx:8, CCR Instruction Format 1st byte 0 4 2nd byte IMM 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 144 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.45 (1) POP (W) POP (POP data) Operation @SP+ Rn Condition Code Pop Data from Stack Assembly-Language Format POP.W Rn Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction restores data from the stack to a 16-bit general register Rn, tests the restored data, and sets condition-code flags according to the result. Available Registers Rn: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode -- Mnemonic POP.W Operands Rn Instruction Format 1st byte 6 D 2nd byte 7 rn 3rd byte 4th byte No. of States 6 Notes POP.W Rn is identical to MOV.W @SP+, Rn. Rev. 3.00 Dec 13, 2004 page 145 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.45 (2) POP (L) POP (POP data) Operation @SP+ ERn Condition Code Pop Data from Stack Assembly-Language Format POP.L ERn Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction restores data from the stack to a 32-bit general register ERn, tests the restored data, and sets condition-code flags according to the result. Available Registers ERn: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode -- Mnemonic POP.L Operands ERn Instruction Format 1st byte 0 1 2nd byte 0 0 3rd byte 6 D 4th byte 7 0 ern No. of States 10 Notes POP.L ERn is identical to MOV.L @SP+, ERn. Rev. 3.00 Dec 13, 2004 page 146 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.46 (1) PUSH (W) PUSH (PUSH data) Operation Rn @-SP Condition Code Push Data on Stack Assembly-Language Format PUSH.W Rn Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction saves data from a 16-bit register Rn onto the stack, tests the saved data, and sets condition-code flags according to the result. Available Registers Rn: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode -- Mnemonic PUSH.W Operands Rn Instruction Format 1st byte 6 D 2nd byte F rn 3rd byte 4th byte No. of States 6 Notes 1. PUSH.W Rn is identical to MOV.W Rn, @-SP. 2. When PUSH.W R7 or PUSH.W E7 is executed, the value saved on the stack is the lower part (R7) or upper part (E7) of the value of ER7 before execution minus two. Rev. 3.00 Dec 13, 2004 page 147 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.46 (2) PUSH (L) PUSH (PUSH data) Operation ERn @-SP Condition Code Push Data on Stack Assembly-Language Format PUSH.L ERn Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the data value is negative; otherwise cleared to 0. Z: Set to 1 if the data value is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction pushes data from a 32-bit register ERn onto the stack, tests the saved data, and sets condition-code flags according to the result. Available Registers ERn: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode -- Mnemonic PUSH.L Operands ERn Instruction Format 1st byte 0 1 2nd byte 0 0 3rd byte 6 D 4th byte F 0 ern No. of States 10 Notes 1. PUSH.L ERn is identical to MOV.L ERn, @-SP. 2. When PUSH.L ER7 is executed, the value saved on the stack is the value of ER7 before execution minus four. Rev. 3.00 Dec 13, 2004 page 148 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.47 (1) ROTL (B) ROTL (ROTate Left) Operation Rd (left rotation) Rd Condition Code Rotate Assembly-Language Format ROTL.B Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 7. Description This instruction rotates the bits in an 8-bit register Rd (destination register) one bit to the left. The most significant bit is rotated to the least significant bit (bit 0), and also copied to the carry flag. MSB LSB . . . . .. C b7 b0 Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic ROTL.B Operands Rd Instruction Format 1st byte 1 2 2nd byte 8 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 149 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.47 (2) ROTL (W) ROTL (ROTate Left) Operation Rd (left rotation) Rd Condition Code Rotate Assembly-Language Format ROTL.W Rd Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 15. Description This instruction rotates the bits in a 16-bit register Rd (destination register) one bit to the left. The most significant bit is rotated to the least significant bit (bit 0), and also copied to the carry flag. MSB LSB . . . . .. C b15 b0 Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic ROTL.W Operands Rd Instruction Format 1st byte 1 2 2nd byte 9 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 150 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.47 (3) ROTL (L) ROTL (ROTate Left) Operation ERd (left rotation) ERd Condition Code Rotate Assembly-Language Format ROTL.L ERd Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 31. Description This instruction rotates the bits in a 32-bit register ERd (destination register) one bit to the left. The most significant bit is rotated to the least significant bit (bit 0), and also copied to the carry flag. MSB LSB . . . . .. C b31 b0 Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic ROTL.L Operands ERd Instruction Format 1st byte 1 2 2nd byte B 0 erd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 151 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.48 (1) ROTR (B) ROTR (ROTate Right) Operation Rd (right rotation) Rd Condition Code Rotate Assembly-Language Format ROTR.B Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Description This instruction rotates the bits in an 8-bit register Rd (destination register) one bit to the right. The least significant bit is rotated to the most significant bit (bit 7), and also copied to the carry flag. MSB LSB . . . . .. b7 b0 C Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic ROTR.B Operands Rd Instruction Format 1st byte 1 3 2nd byte 8 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 152 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.48 (2) ROTR (W) ROTR (ROTate Right) Operation Rd (right rotation) Rd Condition Code Rotate Assembly-Language Format ROTR.W Rd Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Description This instruction rotates the bits in a 16-bit register Rd (destination register) one bit to the right. The least significant bit is rotated to the most significant bit (bit 15), and also copied to the carry flag. MSB LSB . . . . .. b15 b0 C Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic ROTR.W Operands Rd Instruction Format 1st byte 1 3 2nd byte 9 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 153 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.48 (3) ROTR (L) ROTR (ROTate Right) Operation ERd (right rotation) ERd Condition Code Rotate Assembly-Language Format ROTR.L ERd Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Description This instruction rotates the bits in a 32-bit register ERd (destination register) one bit to the right. The least significant bit is rotated to the most significant bit (bit 31), and also copied to the carry flag. MSB LSB . . . . .. b31 b0 C Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic ROTR.L Operands ERd Instruction Format 1st byte 1 3 2nd byte B 0 erd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 154 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.49 (1) ROTXL (B) ROTXL (ROTate with eXtend carry Left) Operation Rd (left rotation through carry bit) Rd Condition Code Rotate through Carry Assembly-Language Format ROTXL.B Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 7. Description This instruction rotates the bits in an 8-bit register Rd (destination register) one bit to the left through the carry flag. The carry flag is rotated into the least significant bit (bit 0). The most significant bit rotates into the carry flag. MSB LSB . . . . .. C b7 b0 Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic ROTXL.B Operands Rd Instruction Format 1st byte 1 2 2nd byte 0 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 155 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.49 (2) ROTXL (W) ROTXL (ROTate with eXtend carry Left) Operation Rd (left rotation through carry bit) Rd Condition Code Rotate through Carry Assembly-Language Format ROTXL.W Rd Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 15. Description This instruction rotates the bits in a 16-bit register Rd (destination register) one bit to the left through the carry flag. The carry flag is rotated into the least significant bit (bit 0). The most significant bit rotates into the carry flag. MSB LSB . . . . .. C b15 b0 Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic ROTXL.W Operands Rd Instruction Format 1st byte 1 2 2nd byte 1 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 156 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.49 (3) ROTXL (L) ROTXL (ROTate with eXtend carry Left) Operation ERd (left rotation through carry bit) ERd Condition Code Rotate through Carry Assembly-Language Format ROTXL.L ERd Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 31. Description This instruction rotates the bits in a 32-bit register ERd (destination register) one bit to the left through the carry flag. The carry flag is rotated into the least significant bit (bit 0). The most significant bit rotates into the carry flag. MSB LSB . . . . .. C b31 b0 Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic ROTXL.L Operands ERd Instruction Format 1st byte 1 2 2nd byte 3 0 erd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 157 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.50 (1) ROTXR (B) ROTXR (ROTate with eXtend carry Right) Operation Rd (right rotation through carry bit) Rd Condition Code Rotate through Carry Assembly-Language Format ROTXR.B Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Description This instruction rotates the bits in an 8-bit register Rd (destination register) one bit to the right through the carry flag. The carry flag is rotated into the most significant bit (bit 7). The least significant bit rotates into the carry flag. MSB LSB . . . . .. b7 b0 C Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic ROTXR.B Operands Rd Instruction Format 1st byte 1 3 2nd byte 0 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 158 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.50 (2) ROTXR (W) ROTXR (ROTate with eXtend carry Right) Operation Rd (right rotation through carry bit) Rd Condition Code Rotate through Carry Assembly-Language Format ROTXR.W Rd Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Description This instruction rotates the bits in a 16-bit register Rd (destination register) one bit to the right through the carry flag. The carry flag is rotated into the most significant bit (bit 15). The least significant bit rotates into the carry flag. MSB LSB . . . . .. b15 b0 C Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic ROTXR.W Operands Rd Instruction Format 1st byte 1 3 2nd byte 1 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 159 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.50 (3) ROTXR (L) ROTXR (ROTate with eXtend carry Right) Operation ERd (right rotation through carry bit) ERd Condition Code Rotate through Carry Assembly-Language Format ROTXR.L ERd Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Description This instruction rotates the bits in a 32-bit register ERd (destination register) one bit to the right through the carry flag. The carry flag is rotated into the most significant bit (bit 31). The least significant bit rotates into the carry flag. MSB LSB . . . . .. b31 b0 C Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic ROTXR.L Operands ERd Instruction Format 1st byte 1 3 2nd byte 3 0 erd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 160 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.51 RTE RTE (ReTurn from Exception) Operation @SP+ CCR @SP+ PC Return from Exception Handling Condition Code I UI H U N Z V C Assembly-Language Format RTE Operand Size -- I: Restored from the corresponding bit on the stack. UI: Restored from the corresponding bit on the stack. H: Restored from the corresponding bit on the stack. U: Restored from the corresponding bit on the stack. N: Restored from the corresponding bit on the stack. Z: Restored from the corresponding bit on the stack. V: Restored from the corresponding bit on the stack. C: Restored from the corresponding bit on the stack. Description This instruction returns from an exception-handling routine by restoring the condition-code register (CCR) and program counter (PC) from the stack. Program execution continues from the address restored to the program counter. The CCR and PC contents at the time of execution of this instruction are lost. Operand Format and Number of States Required for Execution Addressing Mode -- Mnemonic RTE Operands Instruction Format 1st byte 5 6 2nd byte 7 0 3rd byte 4th byte No. of States 10 Rev. 3.00 Dec 13, 2004 page 161 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions RTE RTE (ReTurn from Exception) Notes The stack structure differs between normal mode and advanced mode. Return from Exception Handling Don't care CCR CCR PC Normal mode 23 Undet. 16 15 PC 87 0 Advanced mode 23 16 15 87 0 Rev. 3.00 Dec 13, 2004 page 162 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.52 RTS RTS (ReTurn from Subroutine) Operation @SP+ PC Assembly-Language Format RTS Operand Size -- H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- Return from Subroutine Description This instruction returns from a subroutine by restoring the program counter (PC) from the stack. Program execution continues from the address restored to the program counter. The PC contents at the time of execution of this instruction are lost. Available Registers -- Operand Format and Number of States Required for Execution Addressing Mode -- Instruction Format Mnemonic Operands 1st byte RTS 5 4 2nd byte 3rd byte 7 0 No. of States 4th byte Normal Advanced 8 10 Notes The stack structure and number of states required for execution differ between normal mode and advanced mode. In normal mode, only the lower 16 bits of the program counter are restored. Don't care PC Normal mode 23 Undet. 16 15 PC 87 0 Advanced mode 23 16 15 87 0 Rev. 3.00 Dec 13, 2004 page 163 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.53 (1) SHAL (B) SHAL (SHift Arithmetic Left) Operation Rd (left arithmetic shift) Rd Condition Code Shift Arithmetic Assembly-Language Format SHAL.B Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 7. Description This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the left. The most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0. MSB LSB . . . . .. C b7 b0 0 Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic SHAL.B Operands Rd Instruction Format 1st byte 1 0 2nd byte 8 rd 3rd byte 4th byte No. of States 2 Notes The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag. Rev. 3.00 Dec 13, 2004 page 164 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N Z V C Section 2 Instruction Descriptions 2.2.53 (2) SHAL (W) SHAL (SHift Arithmetic Left) Operation Rd (left arithmetic shift) Rd Condition Code Shift Arithmetic Assembly-Language Format SHAL.W Rd Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 15. Description This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the left. The most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0. MSB LSB . . . . .. C b15 b0 0 Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic SHAL.W Operands Rd Instruction Format 1st byte 1 0 2nd byte 9 rd 3rd byte 4th byte No. of States 2 Notes The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag. Rev. 3.00 Dec 13, 2004 page 165 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N Z V C Section 2 Instruction Descriptions 2.2.53 (3) SHAL (L) SHAL (SHift Arithmetic Left) Operation ERd (left arithmetic shift) ERd Condition Code Shift Arithmetic Assembly-Language Format SHAL.L ERd Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 31. Description This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the left. The most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0. MSB LSB . . . . .. C b31 b0 0 Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic SHAL.L Operands ERd Instruction Format 1st byte 1 0 2nd byte B 0 erd 3rd byte 4th byte No. of States 2 Notes The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag. Rev. 3.00 Dec 13, 2004 page 166 of 258 REJ09B0213-0300 I -- UI -- H -- U -- N Z V C Section 2 Instruction Descriptions 2.2.54 (1) SHAR (B) SHAR (SHift Arithmetic Right) Operation Rd (right arithmetic shift) Rd Condition Code Shift Arithmetic Assembly-Language Format SHAR.B Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 0. Description This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the right. Bit 0 shifts into the carry flag. Bit 7 shifts into itself. Since bit 7 remains unaltered, the sign does not change. MSB LSB . . . . .. b7 b0 C Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic SHAR.B Operands Rd Instruction Format 1st byte 1 1 2nd byte 8 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 167 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.54 (2) SHAR (W) SHAR (SHift Arithmetic Right) Operation Rd (right arithmetic shift) Rd Condition Code Shift Arithmetic Assembly-Language Format SHAR.W Rd Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 0. Description This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the right. Bit 0 shifts into the carry flag. Bit 15 shifts into itself. Since bit 15 remains unaltered, the sign does not change. MSB LSB . . . . .. b15 b0 C Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic SHAR.W Operands Rd Instruction Format 1st byte 1 1 2nd byte 9 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 168 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.54 (3) SHAR (L) SHAR (SHift Arithmetic Right) Operation ERd (right arithmetic shift) ERd Condition Code Shift Arithmetic Assembly-Language Format SHAR.L ERd Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Receives the previous value in bit 0. Description This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the right. Bit 0 shifts into the carry flag. Bit 31 shifts into itself. Since bit 31 remains unaltered, the sign does not change. MSB LSB . . . . .. b31 b0 C Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic SHAR.L Operands ERd Instruction Format 1st byte 1 1 2nd byte B 0 erd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 169 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.55 (1) SHLL (B) SHLL (SHift Logical Left) Operation Rd (left logical shift) Rd Condition Code Shift Logical Assembly-Language Format SHLL.B Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 7. Description This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the left. The most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0. MSB LSB . . . . .. C b7 b0 0 Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic SHLL.B Operands Rd Instruction Format 1st byte 1 0 2nd byte 0 rd 3rd byte 4th byte No. of States 2 Notes The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag. Rev. 3.00 Dec 13, 2004 page 170 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.55 (2) SHLL (W) SHLL (SHift Logical Left) Operation Rd (left logical shift) Rd Condition Code Shift Logical Assembly-Language Format SHLL.W Rd Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 15. Description This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the left. The most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0. MSB LSB . . . . .. C b15 b0 0 Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic SHLL.W Operands Rd Instruction Format 1st byte 1 0 2nd byte 1 rd 3rd byte 4th byte No. of States 2 Notes The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag. Rev. 3.00 Dec 13, 2004 page 171 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.55 (3) SHLL (L) SHLL (SHift Logical Left) Operation ERd (left logical shift) ERd Condition Code Shift Logical Assembly-Language Format SHLL.L ERd Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 31. Description This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the left. The most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0. MSB LSB . . . . .. C b31 b0 0 Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic SHLL.L Operands ERd Instruction Format 1st byte 1 0 2nd byte 3 0 erd 3rd byte 4th byte No. of States 2 Notes The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag. Rev. 3.00 Dec 13, 2004 page 172 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C Section 2 Instruction Descriptions 2.2.56 (1) SHLR (B) SHLR (SHift Logical Right) Operation Rd (right logical shift) Rd Condition Code Shift Logical Assembly-Language Format SHLR.B Rd Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Description This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the right. The least significant bit shifts into the carry flag. The most significant bit (bit 7) is cleared to 0. MSB 0 b7 LSB . . . . .. b0 C Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic SHLR.B Operands Rd Instruction Format 1st byte 1 1 2nd byte 0 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 173 of 258 REJ09B0213-0300 I -- UI -- HU ---- N 0 Z V 0 C Section 2 Instruction Descriptions 2.2.56 (2) SHLR (W) SHLR (SHift Logical Right) Operation Rd (right logical shift) Rd Condition Code Shift Logical Assembly-Language Format SHLR.W Rd Operand Size Word H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Description This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the right. The least significant bit shifts into the carry flag. The most significant bit (bit 15) is cleared to 0. MSB 0 b15 LSB . . . . .. b0 C Available Registers Rd: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic SHLR.W Operands Rd Instruction Format 1st byte 1 1 2nd byte 1 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 174 of 258 REJ09B0213-0300 I -- UI -- HU ---- N 0 Z V 0 C Section 2 Instruction Descriptions 2.2.56 (3) SHLR (L) SHLR (SHift Logical Right) Operation ERd (right logical shift) ERd Condition Code Shift Logical Assembly-Language Format SHLR.L ERd Operand Size Longword H: Previous value remains unchanged. N: Always cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Receives the previous value in bit 0. Description This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the right. The least significant bit shifts into the carry flag. The most significant bit (bit 31) is cleared to 0. MSB 0 b31 LSB . . . . .. b0 C Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic SHLR.L Operands ERd Instruction Format 1st byte 1 1 2nd byte 3 0 erd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 175 of 258 REJ09B0213-0300 I -- UI -- HU ---- N 0 Z V 0 C Section 2 Instruction Descriptions 2.2.57 SLEEP SLEEP (SLEEP) Operation Program execution state power-down mode Assembly-Language Format SLEEP Operand Size -- Description When the SLEEP instruction is executed, the CPU enters a power-down state. Its internal state remains unchanged, but the CPU stops executing instructions and waits for an exception-handling request. When it receives an exception-handling request, the CPU exits the power-down state and begins the exception-handling sequence. Interrupt requests other than NMI cannot end the powerdown state if they are masked in the CPU. Available Registers -- Operand Format and Number of States Required for Execution Addressing Mode -- Mnemonic SLEEP Operands Instruction Format 1st byte 0 1 2nd byte 8 0 3rd byte 4th byte No. of States 2 Power-Down Mode Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Notes For information about the power-down state, see the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 176 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.58 (1) STC (B) STC (STore from Control register) Operation CCR Rd Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- Store CCR Assembly-Language Format STC.B CCR, Rd Operand Size Byte H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction copies the CCR contents to an 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic STC.B Operands CCR, Rd Instruction Format 1st byte 0 2 2nd byte 0 rd 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 177 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.58 (2) STC (W) STC (STore from Control register) Operation CCR (EAd) Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- Store CCR Assembly-Language Format STC.W CCR, Operand Size Word H: N: Z: V: C: Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction copies the CCR contents to a destination location. Although CCR is a byte register, the destination operand is a word operand. The CCR contents are stored at the even address. Available Registers ERd: ER0 to ER7 Rev. 3.00 Dec 13, 2004 page 178 of 258 REJ09B0213-0300 Operand Format and Number of States Required for Execution Instruction Format 1st byte 0 1 4 0 6 9 1 erd 0 6 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte No. of States STC (W) Addressing Mode Mnemonic Operands Register indirect STC.W CCR,@ERd STC.W disp CCR,@(d:16,ERd) 0 1 4 0 6 F 1 erd 0 8 Register indirect with displacement 0 6 B A 0 0 0 disp 1 4 0 7 8 0 erd 0 12 STC.W CCR,@(d:24,ERd) STC (STore from Control register) Register indirect with pre-decrement 0 1 4 0 6 D 1 erd 0 0 8 1 4 0 6 B 0 abs STC.W CCR,@-ERd 8 STC.W CCR,@aa:16 8 Absolute address 0 A 0 0 1 4 0 6 B 0 abs 10 STC.W CCR,@aa:24 Notes Section 2 Instruction Descriptions Store CCR Rev. 3.00 Dec 13, 2004 page 179 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.59 (1) SUB (B) SUB (SUBtract binary) Operation Rd - Rs Rd Condition Code Subtract Binary Assembly-Language Format SUB.B Rs, Rd Operand Size Byte H: Set to 1 if there is a borrow at bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 7; otherwise cleared to 0. Description This instruction subtracts the contents of an 8-bit register Rs (source operand) from the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic SUB.B Operands Rs, Rd Instruction Format 1st byte 1 8 2nd byte rs rd 3rd byte 4th byte No. of States 2 Rev. 3.00 Dec 13, 2004 page 180 of 258 REJ09B0213-0300 I -- UI -- H U -- N Z V C Section 2 Instruction Descriptions SUB (B) SUB (SUBtract binary) Notes The SUB.B instruction can operate only on general registers. Immediate data can be subtracted from general register contents by using the SUBX instruction. Before executing SUBX #xx:8, Rd, first set the Z flag to 1 and clear the C flag to 0. The following coding examples can also be used to subtract nonzero immediate data #IMM. (1) ORC (2) ADD #H'05, CCR SUBX #(IMM-1), Rd #(0-IMM), Rd XORC #H'01, CCR Subtract Binary Rev. 3.00 Dec 13, 2004 page 181 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.59 (2) SUB (W) SUB (SUBtract binary) Operation Rd - (EAs) Rd Condition Code Subtract Binary Assembly-Language Format SUB.W Operand Size Word H: Set to 1 if there is a borrow at bit 11; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 15; otherwise cleared to 0. Description This instruction subtracts a source operand from the contents of a 16-bit register Rd (destination operand) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Mnemonic SUB.W SUB.W Operands #xx:16, Rd Rs, Rd Instruction Format 1st byte 7 1 9 9 2nd byte 3 rs rd rd 3rd byte IMM 4th byte No. of States 4 2 Notes Rev. 3.00 Dec 13, 2004 page 182 of 258 REJ09B0213-0300 I -- UI -- H U -- N Z V C Section 2 Instruction Descriptions 2.2.59 (3) SUB (L) SUB (SUBtract binary) Operation ERd - Assembly-Language Format SUB.L Operand Size Longword H: Set to 1 if there is a borrow at bit 27; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow at bit 31; otherwise cleared to 0. Description This instruction subtracts a source operand from the contents of a 32-bit register ERd (destination operand) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Instruction Format Mnemonic Operands 1st byte SUB.L SUB.L #xx:32, ERd ERs, ERd 7 1 A A 2nd byte 3 0 erd 3rd byte 4th byte 5th byte 6th byte IMM No. of States 6 2 1 ers 0 erd Notes Rev. 3.00 Dec 13, 2004 page 183 of 258 REJ09B0213-0300 I -- UI -- H U -- N Z V C Section 2 Instruction Descriptions 2.2.60 SUBS SUBS (SUBtract with Sign extension) Operation ERd - 1 ERd ERd - 2 ERd ERd - 4 ERd Assembly-Language Format SUBS #1, ERd SUBS #2, ERd SUBS #4, ERd Operand Size Longword H: N: Z: V: C: Subtract Binary Address Data Condition Code I -- UI -- H -- U -- N -- Z -- V -- C -- Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Description This instruction subtracts the immediate value 1, 2, or 4 from the contents of a 32-bit register ERd (destination register). Differing from the SUB instruction, it does not affect the condition-code flags. Available Registers ERd: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Register direct Register direct Register direct Mnemonic SUBS SUBS SUBS Operands #1, ERd #2, ERd #4, ERd Instruction Format 1st byte 1 1 1 B B B 2nd byte 0 8 9 0 erd 0 erd 0 erd 3rd byte 4th byte No. of States 2 2 2 Notes Rev. 3.00 Dec 13, 2004 page 184 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.61 SUBX SUBX (SUBtract with eXtend carry) Operation Rd - (EAs) - C Rd Condition Code Subtract with Borrow Assembly-Language Format SUBX Operand Size Byte H: Set to 1 if there is a borrow from bit 3; otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Set to 1 if an overflow occurs; otherwise cleared to 0. C: Set to 1 if there is a borrow from bit 7; otherwise cleared to 0. Description This instruction subtracts the source operand and carry flag from the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Mnemonic SUBX SUBX Operands #xx:8, Rd Rs, Rd Instruction Format 1st byte B 1 rd E rs 2nd byte IMM rd 3rd byte 4th byte No. of States 2 2 Notes Rev. 3.00 Dec 13, 2004 page 185 of 258 REJ09B0213-0300 I -- UI -- H U -- N Z V C Section 2 Instruction Descriptions 2.2.62 TRAPA TRAPA (TRAP Always) Operation PC @-SP CCR @-SP #x 0 1 2 3 Vector Address Normal Mode H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 Advanced Mode H'000020 to H'000023 H'000024 to H'000027 H'000028 to H'00002B H'00002C to H'00002F Trap Unconditionally Condition Code I 1 UI H *1 -- U -- N -- Z -- V -- C -- I: U: H: N: Z: V: C: Always set to 1. See notes. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Operand Format and Number of States Required for Execution Addressing Mode Register direct Mnemonic TRAPA Operands #x:2 Instruction Format 1st byte 5 7 2nd byte 00 IMM 0 3rd byte 4th byte No. of States 14 Notes 1. CCR bit 6 is set to 1 when used as an interrupt mask bit, but retains its previous value when used as a user bit. 2. The stack and vector structure differ between normal mode and advanced mode. Rev. 3.00 Dec 13, 2004 page 186 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.2.63 (1) XOR (B) XOR (eXclusive OR logical) Operation Rd (EAs) Rd Condition Code Exclusive Logical OR Assembly-Language Format XOR.B Operand Size Byte H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction exclusively ORs the source operand with the contents of an 8-bit register Rd (destination register) and stores the result in the 8-bit register Rd. Available Registers Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Mnemonic XOR.B XOR.B Operands #xx:8, Rd Rs, Rd Instruction Format 1st byte D 1 rd 5 rs 2nd byte IMM rd 3rd byte 4th byte No. of States 2 2 Notes Rev. 3.00 Dec 13, 2004 page 187 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.63 (2) XOR (W) XOR (eXclusive OR logical) Operation Rd (EAs) Rd Condition Code Exclusive Logical OR Assembly-Language Format XOR.W Operand Size Word H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction exclusively ORs the source operand with the contents of a 16-bit register Rd (destination register) and stores the result in the 16-bit register Rd. Available Registers Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7 Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Mnemonic XOR.W XOR.W Operands #xx:16, Rd Rs, Rd Instruction Format 1st byte 7 6 9 5 2nd byte 5 rs rd rd 3rd byte IMM 4th byte No. of States 4 2 Notes Rev. 3.00 Dec 13, 2004 page 188 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.63 (3) XOR (L) XOR (eXclusive OR logical) Operation ERd (EAs) ERd Condition Code Exclusive Logical OR Assembly-Language Format XOR.L Operand Size Longword H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise cleared to 0. Z: Set to 1 if the result is zero; otherwise cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged. Description This instruction exclusively ORs the source operand with the contents of a 32-bit register ERd (destination register) and stores the result in the 32-bit register ERd. Available Registers ERd: ER0 to ER7 ERs: ER0 to ER7 Operand Format and Number of States Required for Execution Addressing Mode Immediate Register direct Instruction Format Mnemonic Operands 1st byte XOR.L XOR.L #xx:32, ERd ERs, ERd 7 0 A 1 2nd byte 5 F 0 erd 0 6 5 3rd byte 4th byte 5th byte 6th byte IMM 0 ers 0 erd No. of States 6 4 Notes Rev. 3.00 Dec 13, 2004 page 189 of 258 REJ09B0213-0300 I -- UI -- HU ---- N Z V 0 C -- Section 2 Instruction Descriptions 2.2.64 XORC XORC (eXclusive OR Control register) Operation CCR #IMM CCR Exclusive Logical OR with CCR Condition Code I UI H U N Z V C Assembly-Language Format XORC #xx:8, CCR Operand Size Byte I: Stores the corresponding bit of the result. UI: Stores the corresponding bit of the result. H: Stores the corresponding bit of the result. U: Stores the corresponding bit of the result. N: Stores the corresponding bit of the result. Z: Stores the corresponding bit of the result. V: Stores the corresponding bit of the result. C: Stores the corresponding bit of the result. Description This instruction exclusively ORs the contents of the condition-code register (CCR) with immediate data and stores the result in the condition-code register. No interrupt requests, including NMI, are accepted immediately after execution of this instruction. Operand Format and Number of States Required for Execution Addressing Mode Immediate Mnemonic XORC Operands #xx:8, CCR Instruction Format 1st byte 0 5 2nd byte IMM 3rd byte 4th byte No. of States 2 Notes Rev. 3.00 Dec 13, 2004 page 190 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.3 Table 2.1 Instruction Set Summary Instruction Set Summary Addressing Modes @ERn+/@-ERn @(d:16,ERn) @(d:24,ERn) @(d:8,PC) Function Instruction @ERn #xx @(d:16,PC) @@aa:8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- @aa:16 @aa:24 @aa:8 Rn Data transfer MOV POP, PUSH MOVFPE, MOVTPE BWL BWL BWL BWL BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- BWL BWL -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- WL -- -- -- -- -- -- -- -- Arithmetic operations ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, DIVXU, MULXS, DIVXS NEG EXTU, EXTS BWL BWL WL B -- -- -- -- BWL B L BWL B BW -- -- BWL WL -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Logic operations AND, OR, XOR NOT BWL BWL -- -- -- BWL BWL B Shift operations Bit manipulation Rev. 3.00 Dec 13, 2004 page 191 of 258 REJ09B0213-0300 -- Section 2 Instruction Descriptions Addressing Modes @ERn+/@-ERn @(d:16,ERn) @(d:24,ERn) @(d:8,PC) Function Instruction @ERn #xx @(d:16,PC) @@aa:8 -- -- -- -- -- -- -- -- @aa:16 @aa:24 @aa:8 Rn Branch Bcc, BSR JMP, JSR RTS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- System control TRAPA, RTE, SLEEP LDC STC ANDC, ORC, XORC NOP B -- B B B -- W W -- W W -- W W -- W W -- -- -- -- W W -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Block data transfer Legend: B: Byte W: Word L: Longword Rev. 3.00 Dec 13, 2004 page 192 of 258 REJ09B0213-0300 -- B Section 2 Instruction Descriptions Table 2.2 Instruction Set (1) Data Transfer Instructions Addressing Mode and Instruction Length (bytes) Size #xx Rn @ERn @(d,ERn) @ERn+/@-ERn @aa @(d,PC) @@aa -- Condition Code No. of States Mnemonic Operation I AdH N Z V C Normal vanced MOV MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd B2 B B 2 2 4 8 2 2 4 6 2 4 8 2 2 4 6 #xx:8Rd8 Rs8Rd8 @ERsRd8 @(d:16,ERs)Rd8 @(d24:,ERs24)Rd8 @ERsRd8,ERs32+1ERs32 @aa:8Rd8 @aa:16Rd8 @aa:24Rd8 Rs8@ERd24 Rd8@(d:16,ERd) Rd8@(d:24,ERd) ERd32-1ERd32,Rs8@ERd Rs8@aa:8 Rs8@aa:16 Rs8@aa:24 #xx:16Rd16 2 2 4 8 2 4 6 2 4 8 2 4 6 Rs16Rd16 @ERs24Rd16 @(d:16,ERs)Rd16 @(d:24,ERs)Rd16 @ERsRd16,ERs32+2@ERd @aa:16Rd16 @aa:24Rd16 Rs16@ERd Rs16@(d:16,ERd) Rs16@(d:24,ERd) ERd32-2ERd32,Rs16@ERd24 Rs16@aa:16 Rs16@aa:24 #xx:32ERd32 2 4 ERs32ERd32 @ERsERd32 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 2 2 4 6 10 6 4 6 8 4 6 10 6 4 6 8 4 2 4 6 10 6 6 8 4 6 8 6 6 8 8 2 8 2 2 4 6 10 6 4 6 8 4 6 10 6 4 6 8 4 2 4 6 10 6 6 8 4 6 10 6 6 8 6 2 8 MOV.B @(d:16, ERs), Rd B MOV.B @(d:24,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:24,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:24,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:24 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd B B B B B B B B B B B B W4 W W MOV.W @(d:16,ERs),Rd W MOV.W @(d:24,ERs),Rd W MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:24,Rd MOV.W Rs,@ERd W W W W MOV.W Rs,@(d:16,ERd) W MOV.W Rs,@(d:24,ERd) W MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:24 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd W W W L6 L L Rev. 3.00 Dec 13, 2004 page 193 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Addressing Mode and Instruction Length (bytes) Size #xx Rn @ERn @(d,ERn) @ERn+/@-ERn @aa @(d,PC) @@aa -- Condition Code No. of States Mnemonic Operation I AdH N Z V C Normal vanced MOV MOV.L @(d:16,ERs),ERd L MOV.L @(d:24,ERs),ERd L MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:24,ERd MOV.L ERs,@ERd L L L L 4 6 10 4 6 8 @(d:16,ERs)ERd32 @(d:24,ERs)ERd32 ERsERd32,ERs32+4@ERs32 @aa:16ERd32 @aa:24ERd32 ERs32@ERd24 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 10 14 10 10 12 8 10 14 10 10 12 6 8 6 8 (6) (6) 10 14 10 10 12 8 10 14 10 10 12 6 10 6 10 (6) (6) MOV.L ERs,@(d:16,ERd) L MOV.L ERs,@(d:24,ERd) L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:24 POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn MOVFPE MOVFPE@aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 L L L W L W L B B 6 10 4 6 8 ERs32@(d:16,ERd) ERs32@(d:24,ERd) ERd32-4ERd32,ERs32@ERd ERs32@aa:16 ERs32@aa:24 2 @SPRn16,SP+2SP 4 @SPERn32,SP+4SP 2 SP-2SP,Rn16@SP 4 SP-4SP,ERn32@SP 4 4 @aa:16Rd (synchronized with E clock) Rs@aa:16 (synchronized with E clock)R Rev. 3.00 Dec 13, 2004 page 194 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions (2) Arithmetic Operation Instructions Addressing Mode and Instruction Length (bytes) Size #xx Rn @ERn @(d,ERn) @ERn+/@-ERn @aa @(d,PC) @@aa -- Condition Code No. of States Mnemonic Operation I AdH N Z V C Normal vanced ADD ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd B2 B W4 W L6 L B2 B L L L B W W L L B B W4 W L6 L B2 B L L L B W W L L B 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rd8+#xx:8Rd8 Rd8+Rs8Rd8 Rd16+#xx:16Rd16 Rd16+Rs16Rd16 ERd32+#xx:32ERd32 ERd32+ERs32ERd32 Rd8+#xx:8+CRd8 Rd8+Rs8+CRd8 ERd32+1ERd32 ERd32+2ERd32 ERd32+4ERd32 Rd8+1Rd8 Rd16+1Rd16 Rd16+2Rd16 ERd32+1ERd32 ERd32+2ERd32 Rd8 decimal adjust Rd8 Rd8-Rs8Rd8 Rd16-#xx:16Rd16 Rd16-Rs16Rd16 ERd32-#xx:32ERd32 ERd32-ERs32ERd32 Rd8-#xx:8-CRd8 Rd8-Rs8-CRd8 Erd32-1ERd32 ERd32-2ERd32 ERd32-4ERd32 Rd8-1Rd8 Rd16-1Rd16 Rd16-2Rd16 ERd32-1ERd32 ERd32-2ERd32 Rd8 decimal adjust Rd8 -- -- 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 -- (1) -- (1) -- (2) -- (2) -- -- ADDX ADDX #xx:8,Rd ADDX Rs,Rd ADDS ADDS.L #1,ERd ADDS.L #2,ERd ADDS.L #4,ERd ------------ ------------ ------------ ---- ---- ---- * -- -- -- -- -- (3) -- -- -- -- -- *-- (3) INC INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd ---- ---- --* -- DAA SUB DAA Rd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd -- (1) -- (1) -- (2) -- (2) -- -- SUBX SUBX.B #xx:8,Rd SUBX.B Rs,Rd SUBS SUBS.L #1,ERd SUBS.L #2,ERd SUBS.L #4,ERd ------------ ------------ ------------ ---- ---- ---- ---- ---- --* DEC DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DAS DAS Rd Rev. 3.00 Dec 13, 2004 page 195 of 258 REJ09B0213-0300 (3) (3) Section 2 Instruction Descriptions Addressing Mode and Instruction Length (bytes) Size #xx Rn @ERn @(d,ERn) @ERn+/@-ERn @aa @(d,PC) @@aa -- Condition Code No. of States Mnemonic Operation I AdH N Z V C Normal vanced NEG NEG.B Rd NEG.W Rd NEG.L ERd B W L B2 B W4 W L6 L B W B W B W 2 2 2 0-Rd8Rd8 0-Rd16Rd16 0-ERd32-ERd32 Rd8-#xx:8 -- -- -- -- -- 2 2 2 2 2 4 2 4 2 14 22 16 24 14 22 2 2 2 2 2 4 2 6 2 14 22 16 24 14 22 CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd 2 Rd8-Rs8 Rd16-#xx:16 -- (1) -- (1) -- (2) -- (2) 2 Rd16-Rs16 ERd32-#xx:32 2 2 2 4 4 2 2 ERd32-ERs32 Rd8 x Rs8Rd16 (unsigned operation) Rd16 x Rs16ERd32 (unsigned operation) Rd8 x Rs8 Rd16 (signed operation) Rd16 x Rs16 ERd32 (signed operation) MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd ------------ ------------ ---- ---- ---- ---- DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd Rd16 / Rs8 Rd16 (RdH: remainder, -- -- (6) (7) -- -- RdL: quotient) (unsigned operation) ERd32 / Rs16 ERd32 -- -- (6) (7) -- -- (Ed: remainder, Rd: quotient) (unsigned operation) Rd16 / Rs8 Rd16 (RdH: remainder, -- -- (8) (7) -- -- RdL: quotient) (signed operation) ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (signed operation) 0 ( DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd B W 4 4 MULXS.W Rs,ERd MULXS MULXS.B Rs,Rd 16 24 16 24 EXTU EXTU.W Rd EXTU.L ERd W L W L 2 2 2 2 ---- 0 ---- 0 ---- 0-- 0-- 0-- 0-- 2 2 2 2 2 2 2 2 EXTS EXTS.W Rd EXTS.L ERd ( Rev. 3.00 Dec 13, 2004 page 196 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions (3) Logic Operation Instructions Addressing Mode and Instruction Length (bytes) Size #xx Rn @ERn @(d,ERn) @ERn+/@-ERn @aa @(d,PC) @@aa -- Condition Code No. of States Mnemonic Operation I AdH N Z V C Normal vanced AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd B2 B W4 W L6 L B2 B W4 W L6 L B2 B W4 W L6 L B W L 4 2 2 2 2 2 4 2 2 4 2 2 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- Rd8 #xx:8Rd8 Rd8 Rs8Rd8 Rd16 #xx:16Rd16 Rd16 Rs16Rd16 ERd32 #xx:32ERd32 ERd32 ERs32ERd32 Rd8 #xx:8Rd8 Rd8 Rs8Rd8 Rd16 #xx:16Rd16 Rd16 Rs16Rd16 ERd32 #xx:32ERd32 ERd32 ERs32ERd32 Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd16#xx:16Rd16 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 Rd8Rd8 Rd16Rd16 Rd32Rd32 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd NOT NOT.B Rd NOT.W Rd NOT.L ERd Rev. 3.00 Dec 13, 2004 page 197 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions (4) Shift Instructions Addressing Mode and Instruction Length (bytes) Size #xx Rn @ERn @(d,ERn) @ERn+/@-ERn @aa @(d,PC) @@aa -- Condition Code No. of States Mnemonic Operation I AdH N Z V C Normal vanced SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd B W L B W L B W L B W L B W L B W L B W L B W L 2 0 2 2 2 2 2 2 0 2 2 2 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 MSB LSB C MSB LSB C MSB LSB C ---- C MSB LSB ---- ---- ---- ---- ---- ---- C MSB LSB ---- ---- ---- MSB LSB C ---- ---- ---- ---- C MSB LSB 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd 0 0 0 0 0 0 0 0 0 0 0 0 0 ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ---- ---- ---- ---- ---- ---- ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd C MSB LSB ---- ---- ---- ---- ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd Rev. 3.00 Dec 13, 2004 page 198 of 258 REJ09B0213-0300 0 0 0 0 0 0 0 0 Section 2 Instruction Descriptions (5) Bit Manipulation Instructions Addressing Mode and Instruction Length (bytes) Size #xx Rn @ERn @(d,ERn) @ERn+/@-ERn @aa @(d,PC) @@aa -- Condition Code No. of States Mnemonic Operation I AdH N Z V C Normal vanced BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 (#xx:3 of Rd8)1 (#xx:3 of @ERd)1 (#xx:3 of @aa:8)1 (Rn8 of Rd8)1 (Rn8 of @ERd)1 (Rn8 of @aa:8)1 (#xx:3 of Rd8)0 (#xx:3 of @ERd)0 (#xx:3 of @aa:8)0 (Rn8 of Rd8)0 (Rn8 of @ERd)0 (Rn8 of @aa:8)0 (#xx:3 of Rd8) (#xx:3 of Rd8) (#xx:3 of @ERd) (#xx:3 of @ERd) (#xx:3 of @aa:8) (#xx:3 of @aa:8) (Rn8 of Rd8) (Rn8 of Rd8) (Rn8 of @ERd) (Rn8 of @ERd) (Rn8 of @aa:8) (Rn8 of @aa:8) (#xx:3 of Rd8)Z (#xx:3 of @ERd)Z (#xx:3 of @aa:8)Z (Rn8 of Rd8)Z (Rn8 of @ERd)Z (Rn8 of @aa:8)Z (#xx:3 of Rd8)C (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of Rd8)C (#xx:3 of @ERd24)C (#xx:3 of @aa:8)C ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------ ------ ------ ------ ------ ------ ---- ---- ---- ---- ---- ---- 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 ---------- ---------- ---------- ---------- ---------- ---------- BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 Rev. 3.00 Dec 13, 2004 page 199 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Addressing Mode and Instruction Length (bytes) Size #xx Rn @ERn @(d,ERn) @ERn+/@-ERn @aa @(d,PC) @@aa -- Condition Code No. of States Mnemonic Operation I AdH N Z V C Normal vanced BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 B B B B B B B B B B B B B B B B B B B B B B B B 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 C(#xx:3 of Rd8) C(#xx:3 of @ERd24) C(#xx:3 of @aa:8) /C(#xx:3 of Rd8) /C(#xx:3 of @ERd24) /C(#xx:3 of @aa:8) C(#xx:3 of Rd8)C C(#xx:3 of @ERd24)C C(#xx:3 of @aa:8)C C (/#xx:3 of Rd8)C C (/#xx:3 of @ERd24)C C (/#xx:3 of @aa:8)C C (#xx:3 of Rd8)C C (#xx:3 of @ERd24)C C (#xx:3 of @aa:8)C C ~(#xx:3 of Rd8)C C ~(#xx:3 of @ERd24)C C ~(#xx:3 of @aa:8)C C (#xx:3 of Rd8)C C (#xx:3 of @ERd24)C C (#xx:3 of @aa:8)C C ~(#xx:3 of Rd8)C C ~(#xx:3 of @ERd24)C C ~(#xx:3 of @aa:8)C ------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 Rev. 3.00 Dec 13, 2004 page 200 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions (6) Branch Instructions Addressing Mode and Instruction Length (bytes) Size #xx Rn @ERn @(d,ERn) @ERn+/@-ERn @aa @(d,PC) @@aa -- Condition Code No. of States Mnemonic Operation Branch condition I AdH N Z V C Normal vanced Bcc BRA d:8(BTd:8) BRA d:16(BTd:16) BRN d:8(BFd:8) BRN d:16(BFd:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 if condition is true then Always PCPC+d else next; Never ------------ ------------ ------------ ------------ 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 CZ=0 ------------ ------------ CZ=1 ------------ ------------ C=0 ------------ ------------ C=1 ------------ ------------ Z=0 ------------ ------------ Z=1 ------------ ------------ V=0 ------------ ------------ V=1 ------------ ------------ N=0 ------------ ------------ N=1 ------------ ------------ NV=0 ------------ ------------ NV=1 ------------ ------------ Z (N V) = 0 -- -- -- -- -- -- ------------ Z (N V) = 1 -- -- -- -- -- -- ------------ Rev. 3.00 Dec 13, 2004 page 201 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Addressing Mode and Instruction Length (bytes) Size #xx Rn @ERn @(d,ERn) @ERn+/@-ERn @aa @(d,PC) @@aa -- Condition Code No. of States Mnemonic Operation Branch condition I AdH N Z V C Normal vanced JMP JMP @ERn JMP @aa:24 JMP @@aa:8 -- -- -- -- -- -- -- -- -- 2 4 2 2 4 2 4 2 PCERn PCaa:24 PC@aa:8 PC@-SP, PCPC+d:8 PC@-SP, PCPC+d:16 PC@-SP, PCERn PC@-SP, PCaa:24 PC@-SP, PC@aa:8 2 PC@SP+ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 4 6 8 6 8 6 8 8 8 4 6 10 8 10 8 10 12 10 BSR BSR d:8 BSR d:16 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 RTS RTS Rev. 3.00 Dec 13, 2004 page 202 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions (7) System Control Instructions Addressing Mode and Instruction Length (bytes) Size #xx Rn @ERn @(d,ERn) @ERn+/@-ERn @aa @(d,PC) @@aa -- Condition Code No. of States Mnemonic Operation I AdH N Z V C Normal vanced TRAPA RTE SLEEP LDC TRAPA #x:2 RTE SLEEP LDC #xx:8,CCR LDC Rs,CCR LDC @ERs,CCR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),CCR LDC @ERs+,CCR LDC @aa:16,CCR LDC @aa:24,CCR -- -- -- B2 B W W W W W W B W W W W W W B2 B2 B2 -- 2 4 6 10 4 6 8 2 4 6 10 4 6 8 2 PC @-SP, CCR@-SP, (1) -- -- -- -- -- 14 10 2 2 2 6 8 12 8 8 10 2 6 8 12 8 8 10 2 2 2 2 14 10 2 2 2 6 8 12 8 8 10 2 6 8 12 8 8 10 2 2 2 2 ------------ -- -------- ------------ ------------ ------------ ------------ ------------ ------------ ------------ STC STC CCR,Rd STC CCR,@ERd STC CCR,@(d:16,ERs) STC CCR,@(d:24,ERs) STC CCR,@-ERs STC CCR,@aa:16 STC CCR,@aa:24 ANDC ORC XORC NOP ANDC #xx:8,CCR ORC #xx:8,CCR XORC #xx:8,CCR NOP Rev. 3.00 Dec 13, 2004 page 203 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions (8) Block Transfer Instructions Addressing Mode and Instruction Length (bytes) Size #xx Rn @ERn @(d,ERn) @ERn+/@-ERn @aa @(d,PC) @@aa -- Condition Code No. of States Mnemonic Operation I AdH N Z V C Normal vanced EEPMOV EEPMOV.B -- 4 if R4L 0 Repeat @R5@R6 R5+1R5 R6+1R6 R4L-1R4L Until R4L = 0 else next; 4 if R4 0 Repeat @R5@R6 R5+1R5 R6+1R6 R4L-1R4L Until R4 = 0 else next; -- -- -- -- -- -- 8+4n*2 8+4n*2 EEPMOV.W -- -- -- -- -- -- -- 8+4n*2 8+4n*2 Notes: 1. 2. (1) (2) (3) (4) (5) (6) (7) (8) The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. For other cases see section 2.6, Number of States Required for Execution. n is the value set in register R4L or R4. Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. Retains its previous value when the result is zero; otherwise cleared to 0. Set to 1 when the adjustment produces a carry; otherwise retains its previous value. The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. Set to 1 when the divisor is negative; otherwise cleared to 0. Set to 1 when the divisor is zero; otherwise cleared to 0. Set to 1 when the quotient is negative; otherwise cleared to 0. Rev. 3.00 Dec 13, 2004 page 204 of 258 REJ09B0213-0300 2.4 Table 2.3 Instruction Codes Size 1st byte B B 0 7 0 7 0 0 0 0 9 0 E 1 7 6 7 0 0 7 7 7 4 5 4 5 4 5 4 5 4 5 4 5 8 4 disp 4 disp 0 disp 8 3 0 3 disp disp 8 2 0 2 disp disp 8 1 0 1 disp disp 8 0 0 disp 0 disp E abs 7 6 0 IMM 0 C 0 erd 0 7 6 0 IMM 0 6 0 IMM rd 6 IMM 1 F 0 6 6 0 ers 0 erd A 6 0 erd IMM 6 rs rd 9 6 rd IMM 6 rs rd rd IMM E rs rd rd IMM B 9 0 erd B 8 0 erd B 0 0 erd A 1 ers 0 erd A 1 0 erd IMM 9 rs rd 9 1 rd IMM 8 rs rd W W L L L L L B B B B W W L L B B B B -- -- -- -- -- -- -- -- -- -- -- 8 rd IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte Instruction Format 10th byte Instruction Mnemonic ADD ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd Instruction Codes ADDX ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 Bcc BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 205 of 258 REJ09B0213-0300 BCS d:8 (BLO d:8) Instruction 1st byte -- -- 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 7 7 7 6 7 7 7 7 7 7 7 7 E C 7 1 IMM 0 erd abs E abs rd 0 7 7 7 7 1 IMM 1 IMM 0 0 C 0 erd 0 6 1 IMM rd 7 7 6 6 1 IMM 1 IMM 0 0 F abs 6 D 0 erd 0 6 2 2 2 rn rd rn rn 0 0 F abs 7 2 D 0 erd 0 7 2 0 IMM 0 IMM 2 0 IMM rd 0 0 8 F 0 disp F disp 8 E 0 disp E disp 8 D 0 disp D disp 8 C 0 disp C disp 8 B 0 disp B disp 8 A 0 disp A disp 8 9 0 disp 9 disp 8 8 0 disp 8 disp 8 7 0 disp 7 disp 8 6 0 disp 6 disp -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B B B B B B B B B B B B 5 8 5 0 disp 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte Mnemonic Size Instruction Format 10th byte Bcc BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 Section 2 Instruction Descriptions BMI d:8 BMI d:16 BGE d:8 Rev. 3.00 Dec 13, 2004 page 206 of 258 REJ09B0213-0300 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 Instruction 1st byte B B B B B B B B B B 7 7 7 7 7 7 6 7 7 7 7 7 7 7 7 6 7 7 5 5 6 7 7 F D 0 erd abs 7 0 IMM C 0 0 rd 0 6 6 7 7 0 IMM 0 IMM 0 0 5 disp disp F abs 6 D 0 erd 0 6 0 rn rd 0 0 rn rn 0 0 F abs 7 0 D 0 erd 0 7 0 0 0 IMM rd 0 IMM 0 IMM 0 0 E abs 7 4 0 IMM 0 C 0 erd 0 7 4 0 IMM 0 4 0 IMM rd F abs 6 1 rn 0 D 0 erd 0 6 1 rn 0 1 rn rd F abs 7 1 0 IMM 0 D 0 erd 0 7 1 0 IMM 0 1 0 IMM rd E abs 7 7 0 IMM 0 C 0 erd 0 7 7 0 IMM 0 7 0 IMM rd B B B B B B B B B B B B B B B B B -- -- B B B 7 E abs 7 5 1 IMM 0 7 C 0 erd 0 7 5 1 IMM 0 7 5 1 IMM rd 7 F abs 6 7 1 IMM 0 7 D 0 erd 0 6 7 1 IMM 0 6 7 1 IMM rd 7 E abs 7 4 1 IMM 0 7 C 0 erd 0 7 4 1 IMM 0 7 4 1 IMM rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte Mnemonic Size Instruction Format 10th byte BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSR BSR d:8 BSR d:16 BST BST #xx:3,Rd BST #xx:3,@ERd Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 207 of 258 REJ09B0213-0300 BST #xx:3,@aa:8 Instruction 1st byte B B B B 6 7 7 7 7 7 A 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 1 1 1 1 0 0 0 B B A 7 7 0 5 D 7 5 7 F rd 0 erd rd rd rd 7 D rd 0 erd B D 4 5 B 5 C 5 3 rs 0 erd 9 9 8 8 F F 1 rs rd 1 D 0 5 3 rs 1 D 0 5 1 rs B F 0 erd rd 0 erd B 7 0 erd B D rd B 5 rd A 0 rd F 0 rd F 0 rd F 1 ers 0 erd A 2 0 erd IMM D rs rd 9 2 rd IMM C rs rd rd IMM E abs 7 5 0 IMM 0 C 0 erd 0 7 5 0 IMM 0 5 0 IMM rd E abs 6 3 rn 0 C 0 erd 0 6 3 rn 0 3 rn rd B B B B B B B W W L L B B B W W L L B W B W -- -- W L W L B W W 7 E abs 7 3 0 IMM 0 7 C 0 erd 0 7 3 0 IMM 0 7 3 0 IMM rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte Mnemonic Size Instruction Format 10th byte BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 CMP CMP.B #xx:8,Rd CMP.B Rs,Rd Section 2 Instruction Descriptions CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd Rev. 3.00 Dec 13, 2004 page 208 of 258 REJ09B0213-0300 CMP.L ERs,ERd DAA DAA Rd DAS DAS Rd DEC DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1,Rd INC.W #2,Rd Instruction 1st byte L L -- -- -- -- -- -- 5 0 0 0 0 0 0 0 0 F 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 9 D 9 A A 8 A 0 rs 0 ers rs abs rs rs rd rd rd 0 0 IMM abs abs C 1 erd rs 8 0 erd 0 E 1 erd rs 6 A 8 1 erd rs disp A rs 0 0 disp A 2 rd 0 0 A 0 rd abs abs rd abs C 0 ers rd 8 0 ers 0 6 A 2 rd E 0 ers rd disp 0 0 disp 8 0 ers rd C rs rd rd IMM 1 4 0 6 B 2 0 0 0 1 4 0 6 B 0 0 abs abs 1 4 0 6 D 0 ers 0 1 4 0 7 8 0 ers 0 6 B 2 0 1 4 0 6 F 0 ers 0 disp 0 0 disp 1 4 0 6 9 0 ers 0 3 0 rs 7 IMM F abs B B W W W W W W B B B B B B B B B B B B B B B B W W W 5 E abs 5 D 0 ern 0 5 B abs 5 A abs 5 9 0 ern 0 0 B F 0 erd 0 B 7 0 erd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte Mnemonic Size Instruction Format 10th byte INC INC.L #1,ERd INC.L #2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,CCR LDC Rs,CCR LDC @ERs,CCR LDC @(d:16,ERs),CCR LDC @(d:24,ERs),CCR LDC @ERs+,CCR LDC @aa:16,CCR LDC @aa:24,CCR MOV MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:24,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:24,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:24,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:24 MOV.W #xx:16,Rd MOV.W Rs,Rd Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 209 of 258 REJ09B0213-0300 MOV.W @ERs,Rd Instruction 1st byte W W W W W W W W W W W L L L L L L L L L L L L L L B B B W B W B W L -- 0 1 7 0 1 7 1 7 8 9 B 0 5 2 rs 5 0 rs rd 0 erd rd rd 0 erd 0 0 1 C 0 0 1 C 0 5 5 6 A C rs 0 2 6 A 4 rd 0 1 0 0 6 B abs abs rs rs rd 0 erd 0 1 0 0 6 B 8 A 0 1 0 0 6 D 0 1 0 0 7 8 0 erd 0 0 ers 0 ers 0 0 0 1 0 0 6 F 1 erd 0 ers 6 1 erd 0 ers abs abs 0 1 0 0 6 9 1 erd 0 ers disp B A 0 ers 0 0 disp 0 1 0 0 6 B 2 0 erd 0 0 1 0 0 6 B 0 0 erd 0 0 1 0 0 6 D 0 ers 0 erd abs abs 0 1 0 0 7 8 0 ers 0 6 B 2 0 1 0 0 6 F 0 ers 0 erd disp 0 erd 0 0 disp 0 1 0 0 6 9 0 ers 0 erd 0 F 1 ers 0 erd 7 A 0 0 erd IMM 6 B A rs 0 0 abs 6 B 8 rs abs 6 D 1 erd rs 7 8 1 erd 0 6 B A rs 0 0 disp 6 F 1 erd rs disp 6 9 1 erd rs 6 B 2 rd 0 0 abs 6 B 0 rd abs 6 D 0 ers rd 7 8 0 ers 0 6 B 2 rd 0 0 disp 6 F 0 ers rd disp 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte Mnemonic Size Instruction Format 10th byte MOV MOV.W @(d:16,ERs),Rd MOV.W @(d:24,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:24,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:24,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:24 Section 2 Instruction Descriptions MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd Rev. 3.00 Dec 13, 2004 page 210 of 258 REJ09B0213-0300 MOV.L @(d:16,ERs),ERd MOV.L @(d:24,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:24,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:24,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:24 MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 MULXS MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOP Instruction 1st byte B W L B B W W 6 7 0 0 6 0 6 0 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 1 1 1 0 B 8 9 B 0 9 0 8 rd rd 0 erd rd rd 0 erd 4 7 0 6 7 0 3 3 0 erd 3 1 rd 3 0 rd 2 3 0 erd 2 1 rd 2 0 rd 3 B 0 erd 3 9 rd 3 8 rd 2 B 0 erd 2 9 rd 2 8 rd 1 0 0 6 D F 0 ern D F rn 1 0 0 6 D 7 0 ern D 7 rn 4 IMM 1 F 0 6 4 0 ers 0 ers A 4 0 erd IMM 4 rs rd L L B W L W L B W L B W L B W L B W L -- -- B W L B W L 7 9 4 rd IMM 1 4 rs rd C rd IMM 1 7 3 0 erd 1 7 1 rd 1 7 0 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte Mnemonic Size Instruction Format 10th byte NOT NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd RTE RTE RTS RTS SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 211 of 258 REJ09B0213-0300 SHAR.L ERd Instruction 1st byte B W L B W L -- B W W W W W W B 1 7 1 7 1 1 1 1 B 1 5 D 1 7 6 7 0 0 5 1 F IMM A 4 0 5 rs rd 0 erd 6 5 IMM 0 ers 0 erd 9 5 rd 5 rs rd IMM rd IMM 7 00 IMM 0 E rs rd rd IMM B 9 0 erd B 8 0 erd B 0 0 erd A 1 ers 0 erd A 3 0 erd IMM 9 rs rd 9 3 rd IMM 8 rs rd W W L L L L L B B -- B B W W L L B 0 1 4 0 6 B A 0 0 0 0 1 4 0 6 B 8 0 abs abs 0 1 4 0 6 D 1 erd 0 0 1 4 0 7 8 0 erd 0 6 B A 0 0 0 0 1 4 0 6 F 1 erd 0 disp disp 0 1 4 0 6 9 1 erd 0 0 2 0 rd 0 1 8 0 1 1 3 0 erd 1 1 1 rd 1 1 0 rd 1 0 3 0 erd 1 0 1 rd 1 0 0 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte Mnemonic Size Instruction Format 10th byte SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP SLEEP STC STC CCR,Rd STC CCR,@ERd STC CCR,@(d:16,ERd) STC CCR,@(d:24,ERd) Section 2 Instruction Descriptions STC CCR,@-ERd STC CCR,@aa:16 STC CCR,@aa:24R Rev. 3.00 Dec 13, 2004 page 212 of 258 REJ09B0213-0300 SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd SUBX SUBX #xx:8,Rd SUBX Rs,Rd TRAPA TRAPA #x:2 XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR Section 2 Instruction Descriptions Legend: IMM: abs: disp: rs, rd, rn: Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, or 24 bits) Displacement (8, 16, or 24 bits) Register field (4 bits specifying an 8-bit or 16-bit register. rs corresponds to operand symbols such as Rs, rd corresponds to operand symbols such as Rd, and rn corresponds to the operand symbol Rn.) ers, erd, ern: Register field (3 bits specifying a 32-bit register. ers corresponds to operand symbols such as ERs, erd corresponds to operand symbols such as ERd, and ern corresponds to the operand symbol ERn.) The register fields specify general registers as follows. Address Register 32-bit Register Register Field 000 001 111 General Register ER0 ER1 ER7 16-bit Register Register Field 0000 0001 0111 1000 1001 1111 General Register R0 R1 R7 E0 E1 E7 8-bit Register Register Field 0000 0001 0111 1000 1001 1111 General Register R0H R1H R7H R0L R1L R7L 2.5 Operation Code Map Tables 2.4 to 2.6 show an operation code map. Rev. 3.00 Dec 13, 2004 page 213 of 258 REJ09B0213-0300 Table 2.4 Operation Code Map (1) Instruction when most significant bit of BH is 0. 2nd byte BH BL Instruction when most significant bit of BH is 1. AL Operation Code: 1st byte AH AL 2 STC Table 2.5 Table 2.5 OR.B XOR.B AND.B Table 2.5 SUB.B SUB.W Table 2.5 Table 2.5 LDC ORG XORG ANDC ADD LDC Table 2.5 Table 2.5 MOV CMP 3 4 5 6 7 8 9 A B C D AH 0 1 E ADDX SUBX F Table 2.5 Table 2.5 0 NOP Table 2.5 1 Table 2.5 Table 2.5 2 MOV.B BHI MULXU OR.W BCLR BOR MOV ADD ADDX CMP SUBX OR XOR AND MOV BTST Table 2.5 BST DIVXU RTS BSR RTE TRAPA Table 2.5 JMP MOV Table 2.5 EEPMOV Table 2.6 BLS BCC BCS BNE BEQ BVC BVS BPL BMI BGE BSR BLT BGT JSR BLE Section 2 Instruction Descriptions 3 Rev. 3.00 Dec 13, 2004 page 214 of 258 REJ09B0213-0300 AND.W XOR.W BIST BLD BXOR BAND BILD BIOR BIXOR BIAND 4 BRA BRN 5 MULXU DIVXU 6 BSET BNOT 7 8 9 A B C D E F Table 2.5 Operation Code Map (2) Operation Code: 2nd byte BH BL AL 1st byte AH BH 2 LDC STC ADD INC ADDS MOV SHLL SHLR ROTXL ROTXR NOT EXTU EXTU ROTR NEG ROTL SHAR SHAL SHAL SHAR ROTL ROTR NEG SUB DEC DEC SUB CMP BHI CMP XOR XOR CMP SUB OR SUB OR BLS BCC BCS BNE AND AND BEQ BVC BVS BPL BMI BGE INC ADDS SLEEP Table 2.6 3 4 5 9 6 7 8 A B C AH AL 01 0 1 D Table 2.6 E F Table 2.6 MOV 0A INC 0B ADDS INC INC 0F DAA 10 SHLL 11 SHLR 12 ROTXL 13 ROTXR 17 NOT EXTS EXTS 1A DEC 1B SUBS DEC DEC 1F DAS 58 BRA BRN BLT BGT BLE 79 MOV ADD Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 215 of 258 REJ09B0213-0300 7A MOV ADD Table 2.6 Operation Code Map (3) 2nd byte BH BL CH CL DH DL 3rd byte 4th byte Operation Code: AL 1st byte AH Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. AHALBHBLCH MULXS DIVXS DIVXS OR BTST BTST BIOR BNOT BNOT BTST BTST BIOR BNOT BNOT BCLR BCLR BOR BCLR BCLR BOR XOR AND CL 1 2 4 5 6 7 8 9 A B C 3 0 D E F 01C05 MULXS 01D05 Section 2 Instruction Descriptions 01F06 7Cr06 *1 Rev. 3.00 Dec 13, 2004 page 216 of 258 REJ09B0213-0300 BXOR BAND BID BILD BIXOR BIAND BST BIST BXOR BAND BID BILD BIXOR BIAND BST BIST 7Cr07 *1 7Dr06 *1 BSET 7Dr07 *1 BSET 7Eaa6 *2 7Eaa7*2 7Faa6*2 BSET 7Faa7 *2 BSET Notes: 1. r is a register field. 2. aa is an absolute address field. Section 2 Instruction Descriptions 2.6 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table 2.8 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table 2.7 indicates the number of states required for each size. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L x SK + M x SM + N x SN Examples: Advanced mode, stack located in external memory, on-chip supporting modules accessed with 8-bit bus width, external devices accessed in three states with one wait state and 16bit bus width. 1. BSET #0, @FFFFC7:8 From table 2.8: I = L = 2, From table 2.7: SI = 4, SL = 3 J = K = M = N= 0 Number of states required for execution = 2 x 4 + 2 x 3 = 14 2. JSR @@30 From table 2.8: I = J = K = 2, From table 2.7: SI = SJ = SK = 4 Number of states required for execution = 2 x 4 + 2 x 4 + 2 x 4 = 24 L=M=N=0 Rev. 3.00 Dec 13, 2004 page 217 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Table 2.7 Number of States per Cycle Access Conditions Cycle On-Chip Supporting 8-Bit Bus On-Chip Module Memory 8-Bit 16-Bit 2-State 3-State Bus Bus Access Access SI SJ SK SL SM SN 1 3 6 1 1 2 4 1 3+m 6+2m 1 1 1 2 6 3 4 6+2m 16-Bit Bus 2-State Access 2 3-State Access 3 + m* Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation Note: * For the MOVFPE and MOVTPE instructions, refer to the relevant microcontroller hardware manual. Legend: m: Number of wait states inserted into external device access Rev. 3.00 Dec 13, 2004 page 218 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Table 2.8 Number of Cycles in Instruction Execution Instruction Fetch Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N Instruction ADD Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ADDS ADDX ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC BAND ANDC #xx:8,CCR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 1 1 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 Rev. 3.00 Dec 13, 2004 page 219 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Branch Address Read J Instruction Fetch Instruction Bcc Mnemonic BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 Stack Operation K Byte Data Access L Word Data Access M Internal Operation N 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 Rev. 3.00 Dec 13, 2004 page 220 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Branch Address Read J Instruction Fetch Instruction BIST Mnemonic BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSR BSR d:8 Advanced Normal BSR d:16 Advanced Normal BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 I 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2 2 1 2 2 Stack Operation K Byte Data Access L Word Data Access M Internal Operation N 2 2 1 1 1 1 2 2 2 2 1 1 2 2 2 2 2 1 2 1 2 2 2 2 Rev. 3.00 Dec 13, 2004 page 221 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Branch Address Read J Instruction Fetch Instruction BTST Mnemonic BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd I 1 2 2 1 2 2 1 2 2 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 2 2 1 1 1 1 1 1 1 Stack Operation K Byte Data Access L Word Data Access M Internal Operation N 1 1 1 1 1 1 12 20 12 20 2n + 2*1 2n + 2*1 Rev. 3.00 Dec 13, 2004 page 222 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Branch Address Read J Instruction Fetch Instruction JMP Mnemonic JMP @ERn JMP @aa:24 JMP @@aa:8 Advanced Normal JSR JSR @ERn Advanced Normal JSR @aa:24 Advanced Normal JSR @@aa:8 Advanced Normal LDC LDC #xx:8,CCR LDC Rs,CCR LDC @ERs,CCR LDC @(d:16,ERs),CCR LDC @(d:24,ERs),CCR LDC @ERs+,CCR LDC @aa:16,CCR LDC @aa:24,CCR MOV MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:24,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:24,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:24,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:24 I 2 2 2 2 2 2 2 2 2 2 1 1 2 3 5 2 3 4 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 Stack Operation K Byte Data Access L Word Data Access M Internal Operation N 2 2 1 2 1 2 1 2 1 2 1 2 2 2 2 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 Rev. 3.00 Dec 13, 2004 page 223 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Branch Address Read J Instruction Fetch Instruction MOV Mnemonic MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:24,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:24,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:24,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:24 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:24,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:24,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:24,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:24 MOVFPE MOVTPE MULXS MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd I 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 2 2 2 2 1 1 Stack Operation K Byte Data Access L Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1*2 1*2 12 20 12 20 2 2 Rev. 3.00 Dec 13, 2004 page 224 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Branch Address Read J Instruction Fetch Instruction NEG Mnemonic NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC POP ORC #xx:8,CCR POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd RTE RTS RTE RTS Advanced Normal I 1 1 1 1 1 1 1 1 1 2 1 3 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 Stack Operation K Byte Data Access L Word Data Access M Internal Operation N 1 2 1 2 2 2 2 2 2 2 1 2 2 2 Rev. 3.00 Dec 13, 2004 page 225 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Branch Address Read J Instruction Fetch Instruction SHAL Mnemonic SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP STC SLEEP STC CCR,Rd STC CCR,@ERd STC CCR,@(d:16,ERd) STC CCR,@(d:24,ERd) STC CCR,@-ERd STC CCR,@aa:16 STC CCR,@aa:24 SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBX SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TRAPA TRAPA #x:2 Advanced Normal I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 5 2 3 4 1 2 1 3 1 1 1 1 2 2 Stack Operation K Byte Data Access L Word Data Access M Internal Operation N 1 1 1 1 1 1 2 2 1 2 2 4 4 Rev. 3.00 Dec 13, 2004 page 226 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Branch Address Read J Instruction Fetch Instruction XOR Mnemonic XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR I 1 1 2 1 3 2 1 Stack Operation K Byte Data Access L Word Data Access M Internal Operation N Notes: 1. When n bytes of data are transferred. Rev. 3.00 Dec 13, 2004 page 227 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.7 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. m Si Di Ri Dn -- 0 1 * Z' C' 31 for longword operands, 15 for word operands, 7 for byte operands The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand Not affected Modified according to the result of the instruction (see definition) Always cleared to 0 Always set to 1 Undetermined (no guaranteed value) Z flag before instruction execution C flag before instruction execution Rev. 3.00 Dec 13, 2004 page 228 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Table 2.9 Instruction ADD Condition Code Modification H N Z V C Definition H=Sm-4*Dm-4+Dm-4*/Rm-4+Sm-4*/Rm-4 N=Rm Z = / R m * / R m - 1 * ... * / R 0 V=Sm*Dm*/Rm+/Sm*/Dm*Rm C=Sm*Dm+Dm*/Rm+Sm*/Rm ADDS ADDX ---- ------ H=Sm-4*Dm-4+Dm-4*/Rm-4+Sm-4*/Rm-4 N=Rm Z = Z ' * / R m * ... * / R 0 V=Sm*Dm*/Rm+/Sm*/Dm*Rm C=Sm*Dm+Dm*/Rm+Sm*/Rm AND -- O -- N=Rm Z = / R m * / R m - 1 * ... * / R 0 ANDC BAND Bcc BCLR BIAND BILD BIOR BIST BIXOR BLD BNOT BOR BSET BSR BST BTST BXOR Stores the corresponding bits of the result C=C'*Dn ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ------ ------ ---- ---- ---- C=C'*/Dn C=/Dn C=C'+/Dn ------ ---- ---- C=C'*/Dn+/C'*/Dn C=Dn ------ ---- C=C'+Dn ------ ------ ------ -- -- Z=/Dn C=C'*/Dn+/C'*Dn ---- Rev. 3.00 Dec 13, 2004 page 229 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Instruction CMP H N Z V C Definition H=Sm-4*/Dm-4+/Dm-4*Rm-4+Sm-4*Rm-4 N=Rm Z = / R m * / R m - 1 * ... * / R 0 V=/Sm*Dm*/Rm+Sm*/Dm*Rm C=Sm*/Dm+/Dm*Rm+Sm*Rm DAA * * N=Rm Z = / R m * / R m - 1 * ... * / R 0 C: decimal arithmetic carry DAS * * N=Rm Z = / R m * / R m - 1 * ... * / R 0 C: decimal arithmetic borrow DEC -- -- N=Rm Z = / R m* / R m - 1 * ... * / R 0 V=Dm*/Rm DIVXS -- -- -- N=Sm*/Dm+/Sm*Dm Z = / S m * / S m - 1 * ... * / S 0 DIVXU -- -- -- N=Sm Z = / S m * / S m - 1 * ... * / S 0 EEPMOV EXTS ---- -- ------ O -- N=Rm Z = / R m * / R m - 1 * ... * / R 0 EXTU INC -- -- O O -- Z = / R m * / R m - 1 * ... * / R 0 -- N=Rm Z = / R m * / R m - 1 * ... * / R 0 V=Dm*/Rm JMP JSR LDC MOV ---- ---- ------ ------ Stores the corresponding bits of the result -- O -- N=Rm Z = / R m * / R m - 1 * ... * / R 0 MOVFPE -- O -- N=Rm Z = / R m * / R m - 1 * ... * / R 0 MOVTPE -- O -- N=Rm Z = / R m * / R m - 1 * ... * / R 0 Rev. 3.00 Dec 13, 2004 page 230 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Instruction MULXS H -- N Z V C Definition -- -- N=R2m Z = R 2 m * R 2 m - 1 * ... * / R 0 MULXU NEG ---- ------ H=Dm-4+Rm-4 N=Rm Z = / R m * / R m - 1 * ... * R 0 V=Dm*Rm C=Dm+Rm NOP NOT ---- -- ------ O -- N=Rm Z = / R m * / R m - 1 * ... * / R 0 OR -- O -- N=Rm Z = / R m * / R m - 1 * .... * / R 0 ORC POP Stores the corresponding bits of the result -- O -- N=Rm Z = / R m * / R m - 1 * ... * / R 0 PUSH -- O -- N=Rm Z = / R m * / R m - 1 * ... * / R 0 ROTL -- O N=Rm Z = / R m * / R m - 1 * ... * / R 0 C=Dm ROTR -- O N=Rm Z = / R m * / R m - 1 * ... * / R 0 C=D0 ROTXL -- O N=Rm Z = / R m * / R m - 1 * ... * / R 0 C=Dm ROTXR -- O N=Rm Z = / R m * / R m - 1 * ... * / R 0 C=D0 RTS RTE ---- ------ Stores the corresponding bits of the result Rev. 3.00 Dec 13, 2004 page 231 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Instruction SHAL H -- N Z V C N=Rm Z = / R m * / R m - 1 * ... * / R 0 V=Dm*/Dm-1+/Dm*Dm-1 C=Dm SHAR -- O N=Rm Z = / R m * / R m - 1 * ... * / R 0 C=D0 SHLL -- O N=Rm Z = / R m * / R m - 1 * ... * / R 0 C=Dm SHLR -- O N=Rm Z = / R m * / R m - 1 * ... * / R 0 C=D0 SLEEP STC SUB ---- ---- ------ ------ H=Sm-4*/Dm-4+/Dm-4*Rm-4+Sm-4*Rm-4 N=Rm Z = / R m * / R m - 1 * ... * / R 0 V=/Sm*Dm*/Rm+Sm*/Dm*Rm C=Sm*/Dm+/Dm*Rm+Sm*Rm SUBS SUBX ---- ------ H=Sm-4*/Dm-4+/Dm-4*Rm-4+Sm-4*Rm-4 N=Rm Z = Z ' * / R m * ... * / R 0 V=/Sm*Dm*/Rm+Sm*/Dm*Rm C=Sm*/Dm+/Dm*Rm+Sm*Rm TRAPA XOR ---- -- ------ O -- N=Rm Z = / R m * / R m - 1 * ... * / R 0 XORC Stores the corresponding bits of the result Definition Rev. 3.00 Dec 13, 2004 page 232 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions 2.8 Bus Cycles During Instruction Execution Table 2.10 indicates the bus cycles during instruction execution by the H8/300H CPU. For the number of states per bus cycle, see table 2.7, Number of States per Cycle. How to read the table: Order of bus cycles Instruction JMP @aa:24 1 R:W 2nd 2 Internal operation (2 states) 3 R:W EA 4 5 6 7 8 End of instruction Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read) Legend R:B R:W W:B W:W 2nd 3rd 4th 5th NEXT EA VEC Byte-size read Word-size read Byte-size write Word-size write Address of 2nd word (3rd and 4th bytes) Address of 3rd word (5th and 6th bytes) Address of 4th word (7th and 8th bytes) Address of 5th word (9th and 10th bytes) Address of next instruction Effective address Vector address Rev. 3.00 Dec 13, 2004 page 233 of 258 REJ09B0213-0300 Section 2 Instruction Descriptions Figure 2.1 shows timing waveforms for the address bus and the RD and WR (HWR or LWR) signals during execution of the above instruction with an 8-bit bus, using 3-state access with no wait states. Address bus RD WR (HWR or LWR) R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction High level Internal operation R:W EA Fetching 1st byte of jump address Fetching 2nd byte of jump address RD, Figure 2.1 Address Bus, RD and WR (HWR or LWR Timing HWR LWR) (8-bit bus, 3-state access, no wait states) Rev. 3.00 Dec 13, 2004 page 234 of 258 REJ09B0213-0300 Table 2.10 Bus States 1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W EA R:W EA R:B EA R:W NEXT R:B EA R:W NEXT R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W 3rd R:W NEXT R:W NEXT 2 3 4 5 6 7 8 Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BRA d:8 (BT d;8) BRN d:8 (BF d;8) BHI d:8 BLS d:8 BCC d:8 (BHS d;8) BCS d:8 (BLO d;8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 235 of 258 REJ09B0213-0300 BMI d:8 Instruction R:W NEXT R:W EA R:W EA R:W EA R:W EA Internal operation, 2 states Internal operation, 2 states Internal operation, 2 states Internal operation, 2 states Internal operation, 2 states Internal operation, 2 states Internal operation, 2 states Internal operation, 2 states Internal operation, 2 states Internal operation, 2 states Internal operation, 2 states Internal operation, 2 states Internal operation, 2 states Internal operation, 2 states Internal operation, 2 states Internal operation, 2 states R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd 1 2 3 4 5 6 7 8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d;16) BRN d:16 (BF d;16) BHI d:16 BLS d:16 Section 2 Instruction Descriptions BCC d:16 (BHS d;16) Rev. 3.00 Dec 13, 2004 page 236 of 258 REJ09B0213-0300 BCS d:16 (BLO d;16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 Instruction R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:B EA R:B EA R:W NEXT R:W NEXT W:B EA W:B EA R:B EA R:B EA R:W NEXT R:W NEXT R:B EA R:B EA R:W NEXT R:W NEXT W:B EA W:B EA R:B EA R:W NEXT R:B EA R:W NEXT W:B EA W:B EA R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT W:B EA R:B EA R:W NEXT W:B EA R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT W:B EA R:B EA R:W NEXT W:B EA R:B EA R:W NEXT W:B EA R:B EA R:W NEXT W:B EA 1 2 3 4 5 6 7 8 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BSET #xx:3,Rd BSET #xx:3,@ERd Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 237 of 258 REJ09B0213-0300 BSET #xx:3,@aa:8 Instruction R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:B EAs *1 R:B EAs *1 R:B EAd *1 R:B EAd *1 R:W NEXT R:W NEXT Internal operation, 12 states Internal operation, 20 states Internal operation, 12 states Internal operation, 20 states R:B EAs *2 R:B EAs *2 W:B EAd *2 W:B EAd *2 R:W NEXT R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT R:B EA R:W NEXT W:B EA R:B EA R:W NEXT W:B EA Internal operation, 2 states Internal operation, 2 states 1 2 3 4 5 6 7 8 BSET Rn,Rd R:B EA R:B EA R:W EA R:W EA R:W EA R:W EA W:W Stack (H) W:W Stack (L) W:W Stack W:W Stack (H) W:W Stack (L) W:W Stack R:W NEXT W:B EA R:W NEXT W:B EA BSET Rn,@ERd BSET Rn,@aa:8 BRS d:8 Normal Advanced BRS d:16 Normal Advanced BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BTST #xx:3,Rd BTST #xx:3,@ERd Section 2 Instruction Descriptions BTST #xx:3,@aa:8 BTST Rn,Rd BTST Rn,@ERd Rev. 3.00 Dec 13, 2004 page 238 of 258 REJ09B0213-0300 BTST Rn,@aa:8 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W Instruction R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 3rd R:B EA R:B EA R:W 4th R:W NEXT R:B EA R:W 3rd R:W 3rd R:W NEXT R:W 4th R:W NEXT R:W 3rd R:W 4th Internal operation, 2 states R:W 3rd R:W NEXT R:W NEXT R:W EA R:W EA R:W 5th R:W EA R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W aa:8 R:W aa:8 W:W Stack (H) R:W aa:8 W:W Stack R:W EA W:W Stack (L) R:W EA Internal operation, 2 states R:W EA W:W Stack (H) Internal operation, 2 states R:W EA W:W Stack W:W Stack (L) R:W EA W:W Stack (H) W:W Stack (L) R:W EA W:W Stack R:W aa:8 R:W aa:8 Internal operation, 2 states R:W EA R:W aa:8 Internal operation, 2 states R:W EA Internal operation, 2 states R:W EA R:W EA 1 2 3 4 5 6 7 8 EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 JMP @@aa:8 Normal Advanced JSR @ERn Normal Advanced JSR @aa:24 Normal Advanced JSR @@aa:8 Normal Advanced LDC #xx:8,CCR LDC Rs,CCR LDC @ERs,CCR LDC @(d:16,ERs),CCR LDC @(d:24,ERs),CCR LDC @ERs+,CCR LDC @aa:16,CCR LDC @aa:24,CCR MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 239 of 258 REJ09B0213-0300 MOV.B @(d:24,ERs),Rd Instruction R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 3rd R:W 3rd R:W NEXT R:W EA R:W NEXT R:W 4th Internal operation, 2 states R:W EA+2 R:W EA R:W 5th R:W EA R:W EA+2 R:W NEXT R:W EA+2 R:W EA R:W EA+2 R:W 3rd R:W NEXT R:W 3rd R:W NEXT R:W NEXT W:W EA W:W EA Internal operation, 2 states W:W EA R:W 3rd R:E 4th R:W NEXT W:W EA R:W NEXT W:W EA W:W EA R:W 3rd R:W NEXT R:B EA R:W NEXT R:W EA Internal operation, 2 states R:W EA R:W 3rd R:W 4th R:W NEXT R:W EA R:W NEXT R:W EA R:W EA R:W NEXT R:W 3rd R:W NEXT W:B EA R:W NEXT W:B EA W:B EA Internal operation, 2 states W:B EA R:W 3rd R:W 4th R:W NEXT W:B EA R:W NEXT W:B EA W:B EA R:W 3rd R:W NEXT R:B EA R:W NEXT R:B EA R:B EA Internal operation, 2 states R:B EA 1 2 3 4 5 6 7 8 MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:24,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:24,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 Section 2 Instruction Descriptions MOV.B Rs,@aa:24 MOV.W #xx:16,Rd MOV.W Rs,Rd Rev. 3.00 Dec 13, 2004 page 240 of 258 REJ09B0213-0300 MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:24,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:24,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:24,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:24 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:24,ERs),ERd MOV.L @ERs+,ERd Instruction R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W NEXT Internal operation, 2 states R:W Stack Internal operation, 2 states R:W Stack (H) R:W Stack (L) R:W NEXT R:W rd R:W NEXT R:W NEXT Internal operation, 20 states Internal operation, 12 states R:W NEXT R:W NEXT Internal operation, 12 states Internal operation, 20 states Internal operation, 2 states W:B *3 EA Internal operation, 2 states R:W *3 EA R:W 3rd R:W 4th R:W NEXT W:W EA W:W EA+2 R:W 3rd R:W NEXT W:W EA W:W EA+2 R:W NEXT Internal operation, 2 states W:W EA W:W EA+2 R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA W:W EA+2 R:W 3rd R:W NEXT W:W EA W:W EA+2 R:W NEXT W:W EA W:W EA+2 R:W 3rd R:W 4th R:W NEXT R:W EA R:W EA+2 R:W 3rd R:W NEXT R:W EA R:W EA+2 1 2 3 4 5 6 7 8 MOV.L @aa:16,ERd MOV.L @aa:24,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:24,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:24 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR POP.W Rn Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 241 of 258 REJ09B0213-0300 POP.L ERn Instruction R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W Stack (H) R:W Stack (L) Internal operation, 2 states R:W Stack Internal operation, 2 states R:W (*4) R:W (*4) R:W Stack (H) R:W Stack (L) Internal operation, 2 states R:W (*4) R:W NEXT Internal operation, 2 states W:W Stack (L) W:W Stack (H) Internal operation, 2 states W:W Stack 1 2 3 4 5 6 7 8 PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL.B Rd ROTXL.W Rd Section 2 Instruction Descriptions ROTXL.L ERd ROTXR.B Rd ROTXR.W Rd Rev. 3.00 Dec 13, 2004 page 242 of 258 REJ09B0213-0300 ROTXR.L ERd RTE RTS Normal Advanced SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP STC CCR,Rd Instruction 8 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W VEC R:W VEC R:W (*6) R:W (*6) Internal operation, 2 states Internal operation, 2 states R:W VEC+2 Internal operation, 2 states R:W (*5) Internal operation, 2 states W:W stack (L) W:W stack (L) R:W (*5) W:W stack (H) W:W stack (H) R:W VEC R:W VEC Internal operation, 2 states R:W VEC+2 R:W (*7) Internal operation, 2 states R:W (*7) R:W NEXT R:W 3rd R:W NEXT R:W NEXT Internal operation, 2 states W:W Stack (L) W:W Stack (H) R:W VEC Internal operation, 2 states W:W Stack (L) W:W Stack (H) R:W VEC Internal operation, 2 states R:W VEC+2 R:W (*7) Internal operation, 2 states R:W (*7) R:W 3rd R:W NEXT R:W NEXT R:W 3rd R:W 4th R:W NEXT W:W EA R:W 3rd R:W NEXT W:W EA R:W NEXT Internal operation, 2 states W:W EA R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA R:W 3rd R:W NEXT W:W EA R:W NEXT W:W EA 1 2 3 4 5 6 7 STC CCR,@ERd STC CCR,@(d:16,ERd) STC CCR,@(d:24,ERd) STC CCR,@-ERd STC CCR,@aa:16 STC CCR,@aa:24 SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TRAPA #x:2 Normal Advanced XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC #xx:8,CCR Reset exception handling Normal Advanced Interrupt exception handling Normal Section 2 Instruction Descriptions Rev. 3.00 Dec 13, 2004 page 243 of 258 REJ09B0213-0300 Advanced Section 2 Instruction Descriptions Notes: 1. EAs is the contents of ER5. EAd is the contents of R6. 2. EAs is the contents of ER5. EAd is the contents of R6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. 3. The number of states required for byte read or write varies from 9 to 16. 4. Starting address after return. 5. Starting address of the program. 6. Prefetch address, equal to two plus the PC value pushed on the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. 7. Starting address of the interrupt-handling routine. 8. NEXT: Next address after the current instruction. 2nd: Address of the second word of the current instruction. 3rd: Address of the third word of the current instruction. 4th: Address of the fourth word of the current instruction. 5th: Address of the fifth word of the current instruction. EA: Effective address. VEC: Vector address. Rev. 3.00 Dec 13, 2004 page 244 of 258 REJ09B0213-0300 Section 3 Processing States Section 3 Processing States 3.1 Overview The CPU has five main processing states: the program execution state, exception handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 3.1 shows a diagram of the processing states. Figure 3.2 indicates the state transitions. For details, refer to the relevant microcontroller hardware manual. Processing states Program execution state The CPU executes program instructions in sequence. Exception-handling state A transient state in which the CPU executes a hardware sequence (saving the program counter and condition-code register, fetching a vector, etc.) in response to a reset, interrupt, or other exception. Bus-released state The external bus has been released in response to an external or internal bus request signal. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Power-down state Some or all clock signals are stopped to conserve power. Sleep mode Software standby mode Hardware standby mode Figure 3.1 Processing States Rev. 3.00 Dec 13, 2004 page 245 of 258 REJ09B0213-0300 Section 3 Processing States End of bus-released state Bus request Program execution state P ith =1 EE w BY SL on SS cti = 0 ith tru BY nw in s SS ctio stru P in re End lea o fe se f b xc u ep Bu d st sRe tio at sr qu e nh eq es an t fo ue dl i st re ng xc ep tio nh an dli ng SL EE Bus-released state Sleep mode Bus request completion Bus request En do Inte est equ pt r rr u External interrupt Exception-handling state Software standby mode RES high Reset state*1 STBY high, RES low Hardware standby mode Power-down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. Figure 3.2 State Transitions 3.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 3.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address. In interrupt exception handling the CPU references the stack pointer (ER7) and saves the program counter and condition-code register. Rev. 3.00 Dec 13, 2004 page 246 of 258 REJ09B0213-0300 Section 3 Processing States 3.3.1 Types of Exception Handling and Their Priority Exception handling is performed for resets, interrupts, and trap instructions. Table 3.1 indicates the types of exception handling and their priority. Table 3.1 Priority High Exception Handling Types and Priority Type of Exception Reset Detection Timing Synchronized with clock End of instruction execution (see note) Start of Exception Handling Exception handling starts immediately when RES changes from low to high When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Exception handling starts when a trap (TRAPA) instruction is executed Interrupt Trap instruction Low When TRAPA instruction is executed Note: Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. Figure 3.3 classifies the exception sources. For further details about exception sources, vector numbers, and vector addresses refer to the relevant microcontroller hardware manual. Reset External interrupts Exception sources Interrupt Internal interrupts (from on-chip supporting modules) Trap instruction Figure 3.3 Classification of Exception Sources Rev. 3.00 Dec 13, 2004 page 247 of 258 REJ09B0213-0300 Section 3 Processing States 3.3.2 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Then, if RES goes high again, reset exception handling starts when the reset condition is satisfied. Refer to the relevant microcontroller hardware manual for details about the reset condition. When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during the reset exception-handling sequence and immediately after it ends. Interrupt Exception Handling and Trap Instruction Exception Handling: When these exceptionhandling sequences begin, the CPU references the stack pointer (ER7) and pushes the program counter and condition-code register on the stack. Next, if the UE bit in the system control register (SYSCR) is set to 1, the CPU sets the I bit in the condition-code register to 1. If the UE bit is cleared to 0, the CPU sets both the I bit and the UI bit in the condition-code register to 1. Then the CPU fetches a start address from the exception vector table and execution branches to that address. The program-counter value pushed on the stack and the start address fetched from the vector table are 16 bits long in normal mode and 24 bits long in advanced mode. Figure 3.4 shows the stack after the exception-handling sequence. Rev. 3.00 Dec 13, 2004 page 248 of 258 REJ09B0213-0300 Section 3 Processing States SP - 4 SP - 3 SP - 2 SP - 1 SP (ER7) Stack area SP (ER7) SP + 1 SP + 2 SP + 3 SP + 4 CCR CCR* PCH PCL Even address Before exception handling starts Pushed on stack After exception handling ends (a) Stack structure in normal mode SP - 4 SP - 3 SP - 2 SP - 1 SP (ER7) Stack area SP (ER7) SP + 1 SP + 2 SP + 3 SP + 4 CCR PCE PCH PCL Even address Before exception handling starts Pushed on stack After exception handling ends (b) Stack structure in advanced mode Legend: PCE: Program counter (PC) bits 23 to 16 PCH: Program counter (PC) bits 15 to 8 PCL: Program counter (PC) bits 7 to 0 CCR: Condition code register SP: Stack pointer Notes: * Ignored at return. 1. PC is the address of the first instruction executed after the return from the exception-handling routine. 2. Registers must be saved and restored by word access or longword access, starting at an even address. Figure 3.4 Stack Structure after Exception Handling Rev. 3.00 Dec 13, 2004 page 249 of 258 REJ09B0213-0300 Section 3 Processing States 3.4 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts except for internal operations. For further details, refer to the relevant microcontroller hardware manual. For further details, refer to the relevant microcontroller hardware manual. 3.5 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. The I bit in the condition-code register is set to 1 by a reset. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. 3.6 Power-Down State In the power-down state the CPU stops operating to conserve power. There are three modes: sleep mode, software standby mode, and hardware standby mode. For details, refer to the relevant microcontroller hardware manual. 3.6.1 Sleep Mode A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) is cleared to 0. CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. 3.6.2 Software Standby Mode A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit is set to 1. The CPU and clock halt and all on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. Rev. 3.00 Dec 13, 2004 page 250 of 258 REJ09B0213-0300 Section 3 Processing States 3.6.3 Hardware Standby Mode A transition to hardware standby mode is made when the STBY input goes low. As in software standby mode, the CPU and clock halt and the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. Rev. 3.00 Dec 13, 2004 page 251 of 258 REJ09B0213-0300 Section 3 Processing States Rev. 3.00 Dec 13, 2004 page 252 of 258 REJ09B0213-0300 Section 4 Basic Timing Section 4 Basic Timing 4.1 Overview The CPU is driven by a clock, denoted by the symbol . One cycle of the clock is referred to as a "state." The memory cycle or bus cycle consists of two or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and external devices. Refer to the relevant microcontroller hardware manual for details. 4.2 On-Chip Memory (RAM, ROM) For high-speed processing, on-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and word access. Figure 4.1 shows the on-chip memory access cycle. Figure 4.2 shows the pin states. Bus cycle T1 state Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Write data Read data Address T2 state Figure 4.1 On-Chip Memory Access Cycle Rev. 3.00 Dec 13, 2004 page 253 of 258 REJ09B0213-0300 Section 4 Basic Timing Bus cycle T1 state T2 state Address bus AS High RD High WR (HWR or LWR) High Data bus high-impedance state Address Figure 4.2 Pin States during On-Chip Memory Access Rev. 3.00 Dec 13, 2004 page 254 of 258 REJ09B0213-0300 Section 4 Basic Timing 4.3 On-Chip Supporting Modules The on-chip supporting modules are accessed in three states. The data bus is 8 bits or 16 bits wide. Figure 4.3 shows the access timing for the on-chip supporting modules. Figure 4.4 shows the pin states. Bus cycle T1 state T2 state T3 state Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Address Read data Write data Figure 4.3 On-Chip Supporting Module Access Cycle Rev. 3.00 Dec 13, 2004 page 255 of 258 REJ09B0213-0300 Section 4 Basic Timing Bus cycle T1 state T2 state T3 state Address bus AS High RD High WR (HWR or LWR) High Data bus high-impedance state Address Figure 4.4 Pin States during On-Chip Supporting Module Access 4.4 External Data Bus The external data bus is accessed with 8-bit or 16-bit bus width in two or three states. Figure 4.5 shows the read timing for two-state or three-state access. Figure 4.6 shows the write timing for two-state or three-state access. In three-state access, wait states can be inserted by the wait-state controller or other means. For further details refer to the relevant microcontroller hardware manual. Rev. 3.00 Dec 13, 2004 page 256 of 258 REJ09B0213-0300 Section 4 Basic Timing Read cycle T1 state T2 state Address bus Address AS RD Data bus Read data (two-state access) Read cycle T1 state T2 state T3 state Address bus Address AS RD Data bus (three-state access) Read data Figure 4.5 External Device Access Timing (1) Read Timing Rev. 3.00 Dec 13, 2004 page 257 of 258 REJ09B0213-0300 Section 4 Basic Timing Write cycle T1 state T2 state Address bus Address AS WR (HWR or LWR) Data bus Write data (a) Two-state access Write cycle T1 state T2 state T3 state Address bus Address AS WR (HWR or LWR) Data bus Write data (b) Three-state access Figure 4.6 External Device Access Timing (2) Write Timing Rev. 3.00 Dec 13, 2004 page 258 of 258 REJ09B0213-0300 Renesas 16-Bit Single-Chip Microcomputer Software Manual H8/300H Series Publication Date: 1st Edition, August 1993 Rev.3.00, December 13, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. (c) 2004. Renesas Technology Corp. All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 http://www.renesas.com Colophon 2.0 H8/300H Series Software Manual |
Price & Availability of H8300H
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |